1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright Altera Corporation (C) 2026. All rights reserved. 4 */ 5 6#include "socfpga_stratix10_socdk.dtsi" 7 8/ { 9 model = "SoCFPGA Stratix 10 SoCDK eMMC daughter board"; 10 compatible = "altr,socfpga-stratix10-socdk-emmc", 11 "altr,socfpga-stratix10-socdk", 12 "altr,socfpga-stratix10"; 13}; 14 15&gmac2 { 16 status = "okay"; 17 /* PHY delays is configured via skew properties */ 18 phy-mode = "rgmii"; 19 phy-handle = <&phy0>; 20 21 max-frame-size = <9000>; 22 23 mdio0 { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 compatible = "snps,dwmac-mdio"; 27 phy0: ethernet-phy@4 { 28 reg = <4>; 29 30 txd0-skew-ps = <0>; /* -420ps */ 31 txd1-skew-ps = <0>; /* -420ps */ 32 txd2-skew-ps = <0>; /* -420ps */ 33 txd3-skew-ps = <0>; /* -420ps */ 34 rxd0-skew-ps = <420>; /* 0ps */ 35 rxd1-skew-ps = <420>; /* 0ps */ 36 rxd2-skew-ps = <420>; /* 0ps */ 37 rxd3-skew-ps = <420>; /* 0ps */ 38 txen-skew-ps = <0>; /* -420ps */ 39 txc-skew-ps = <900>; /* 0ps */ 40 rxdv-skew-ps = <420>; /* 0ps */ 41 rxc-skew-ps = <1680>; /* 780ps */ 42 }; 43 }; 44}; 45 46&mmc { 47 status = "okay"; 48 cap-mmc-highspeed; 49 broken-cd; 50 bus-width = <4>; 51 clk-phase-sd-hs = <0>, <135>; 52}; 53 54&i2c2 { 55 status = "okay"; 56 clock-frequency = <100000>; 57 i2c-sda-falling-time-ns = <890>; /* hcnt */ 58 i2c-scl-falling-time-ns = <890>; /* lcnt */ 59 60 adc@14 { 61 compatible = "lltc,ltc2497"; 62 reg = <0x14>; 63 vref-supply = <&ref_033v>; 64 }; 65 66 temp@4c { 67 compatible = "maxim,max1619"; 68 reg = <0x4c>; 69 }; 70 71 eeprom@51 { 72 compatible = "atmel,24c32"; 73 reg = <0x51>; 74 pagesize = <32>; 75 }; 76 77 rtc@68 { 78 compatible = "dallas,ds1339"; 79 reg = <0x68>; 80 }; 81}; 82