1*7d1f68e8SStefan Dösinger// SPDX-License-Identifier: GPL-2.0-only 2*7d1f68e8SStefan Dösinger/* 3*7d1f68e8SStefan Dösinger * Copyright (c) 2026 Stefan Dösinger <stefandoesinger@gmail.com> 4*7d1f68e8SStefan Dösinger */ 5*7d1f68e8SStefan Dösinger 6*7d1f68e8SStefan Dösinger#include <dt-bindings/interrupt-controller/arm-gic.h> 7*7d1f68e8SStefan Dösinger 8*7d1f68e8SStefan Dösinger/ { 9*7d1f68e8SStefan Dösinger #address-cells = <1>; 10*7d1f68e8SStefan Dösinger #size-cells = <1>; 11*7d1f68e8SStefan Dösinger 12*7d1f68e8SStefan Dösinger cpus { 13*7d1f68e8SStefan Dösinger #address-cells = <1>; 14*7d1f68e8SStefan Dösinger #size-cells = <0>; 15*7d1f68e8SStefan Dösinger 16*7d1f68e8SStefan Dösinger cpu@0 { 17*7d1f68e8SStefan Dösinger device_type = "cpu"; 18*7d1f68e8SStefan Dösinger compatible = "arm,cortex-a53"; 19*7d1f68e8SStefan Dösinger reg = <0>; 20*7d1f68e8SStefan Dösinger }; 21*7d1f68e8SStefan Dösinger }; 22*7d1f68e8SStefan Dösinger 23*7d1f68e8SStefan Dösinger /* Base bus clock and default for the UART. It will be replaced once a clock driver has 24*7d1f68e8SStefan Dösinger * been added. 25*7d1f68e8SStefan Dösinger */ 26*7d1f68e8SStefan Dösinger uartclk: uartclk-26000000 { 27*7d1f68e8SStefan Dösinger #clock-cells = <0>; 28*7d1f68e8SStefan Dösinger compatible = "fixed-clock"; 29*7d1f68e8SStefan Dösinger clock-frequency = <26000000>; 30*7d1f68e8SStefan Dösinger }; 31*7d1f68e8SStefan Dösinger 32*7d1f68e8SStefan Dösinger timer { 33*7d1f68e8SStefan Dösinger compatible = "arm,armv7-timer"; 34*7d1f68e8SStefan Dösinger interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 35*7d1f68e8SStefan Dösinger <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 36*7d1f68e8SStefan Dösinger <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 37*7d1f68e8SStefan Dösinger <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 38*7d1f68e8SStefan Dösinger clock-frequency = <26000000>; 39*7d1f68e8SStefan Dösinger interrupt-parent = <&gic>; 40*7d1f68e8SStefan Dösinger /* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the 41*7d1f68e8SStefan Dösinger * arm timer at all. Since this is a single CPU system I don't think it 42*7d1f68e8SStefan Dösinger * really matters that the offset is random though. 43*7d1f68e8SStefan Dösinger */ 44*7d1f68e8SStefan Dösinger arm,cpu-registers-not-fw-configured; 45*7d1f68e8SStefan Dösinger }; 46*7d1f68e8SStefan Dösinger 47*7d1f68e8SStefan Dösinger soc { 48*7d1f68e8SStefan Dösinger #address-cells = <1>; 49*7d1f68e8SStefan Dösinger #size-cells = <1>; 50*7d1f68e8SStefan Dösinger compatible = "simple-bus"; 51*7d1f68e8SStefan Dösinger interrupt-parent = <&gic>; 52*7d1f68e8SStefan Dösinger ranges; 53*7d1f68e8SStefan Dösinger 54*7d1f68e8SStefan Dösinger /* The GIC has a non-standard way of configuring ints between level-low/level 55*7d1f68e8SStefan Dösinger * high or rising edge/falling edge at 0xf2202070 and onwards. See AP_INT_MODE_BASE 56*7d1f68e8SStefan Dösinger * and AP_PPI_MODE_REG in the ZTE kernel, although the offsets in the kernel source 57*7d1f68e8SStefan Dösinger * seem wrong. 58*7d1f68e8SStefan Dösinger * 59*7d1f68e8SStefan Dösinger * Everything defaults to active-high/rising edge, but the timer is active-low. We 60*7d1f68e8SStefan Dösinger * currently rely on the boot loader to change timer IRQs to active-low for us for 61*7d1f68e8SStefan Dösinger * now. 62*7d1f68e8SStefan Dösinger */ 63*7d1f68e8SStefan Dösinger gic: interrupt-controller@f2000000 { 64*7d1f68e8SStefan Dösinger compatible = "arm,gic-v3"; 65*7d1f68e8SStefan Dösinger interrupt-controller; 66*7d1f68e8SStefan Dösinger #interrupt-cells = <3>; 67*7d1f68e8SStefan Dösinger #address-cells = <1>; 68*7d1f68e8SStefan Dösinger #size-cells = <1>; 69*7d1f68e8SStefan Dösinger reg = <0xf2000000 0x10000>, 70*7d1f68e8SStefan Dösinger <0xf2040000 0x20000>; 71*7d1f68e8SStefan Dösinger }; 72*7d1f68e8SStefan Dösinger 73*7d1f68e8SStefan Dösinger uart0: serial@131000 { 74*7d1f68e8SStefan Dösinger compatible = "arm,pl011", "arm,primecell"; 75*7d1f68e8SStefan Dösinger arm,primecell-periphid = <0x0018c011>; 76*7d1f68e8SStefan Dösinger reg = <0x00131000 0x1000>; 77*7d1f68e8SStefan Dösinger interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 78*7d1f68e8SStefan Dösinger clocks = <&uartclk>, <&uartclk>; 79*7d1f68e8SStefan Dösinger clock-names = "uartclk", "apb_pclk"; 80*7d1f68e8SStefan Dösinger status = "disabled"; 81*7d1f68e8SStefan Dösinger }; 82*7d1f68e8SStefan Dösinger 83*7d1f68e8SStefan Dösinger uart1: serial@1408000 { 84*7d1f68e8SStefan Dösinger compatible = "arm,pl011", "arm,primecell"; 85*7d1f68e8SStefan Dösinger arm,primecell-periphid = <0x0018c011>; 86*7d1f68e8SStefan Dösinger reg = <0x01408000 0x1000>; 87*7d1f68e8SStefan Dösinger interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 88*7d1f68e8SStefan Dösinger clocks = <&uartclk>, <&uartclk>; 89*7d1f68e8SStefan Dösinger clock-names = "uartclk", "apb_pclk"; 90*7d1f68e8SStefan Dösinger status = "disabled"; 91*7d1f68e8SStefan Dösinger }; 92*7d1f68e8SStefan Dösinger 93*7d1f68e8SStefan Dösinger uart2: serial@140d000 { 94*7d1f68e8SStefan Dösinger compatible = "arm,pl011", "arm,primecell"; 95*7d1f68e8SStefan Dösinger arm,primecell-periphid = <0x0018c011>; 96*7d1f68e8SStefan Dösinger reg = <0x0140d000 0x1000>; 97*7d1f68e8SStefan Dösinger interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 98*7d1f68e8SStefan Dösinger clocks = <&uartclk>, <&uartclk>; 99*7d1f68e8SStefan Dösinger clock-names = "uartclk", "apb_pclk"; 100*7d1f68e8SStefan Dösinger status = "disabled"; 101*7d1f68e8SStefan Dösinger }; 102*7d1f68e8SStefan Dösinger }; 103*7d1f68e8SStefan Dösinger}; 104