1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2026 Stefan Dösinger <stefandoesinger@gmail.com> 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu@0 { 17 device_type = "cpu"; 18 compatible = "arm,cortex-a53"; 19 reg = <0>; 20 }; 21 }; 22 23 /* Base bus clock and default for the UART. It will be replaced once a clock driver has 24 * been added. 25 */ 26 uartclk: uartclk-26000000 { 27 #clock-cells = <0>; 28 compatible = "fixed-clock"; 29 clock-frequency = <26000000>; 30 }; 31 32 timer { 33 compatible = "arm,armv7-timer"; 34 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 35 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 36 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 37 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 38 clock-frequency = <26000000>; 39 interrupt-parent = <&gic>; 40 /* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the 41 * arm timer at all. Since this is a single CPU system I don't think it 42 * really matters that the offset is random though. 43 */ 44 arm,cpu-registers-not-fw-configured; 45 }; 46 47 soc { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 compatible = "simple-bus"; 51 interrupt-parent = <&gic>; 52 ranges; 53 54 /* The GIC has a non-standard way of configuring ints between level-low/level 55 * high or rising edge/falling edge at 0xf2202070 and onwards. See AP_INT_MODE_BASE 56 * and AP_PPI_MODE_REG in the ZTE kernel, although the offsets in the kernel source 57 * seem wrong. 58 * 59 * Everything defaults to active-high/rising edge, but the timer is active-low. We 60 * currently rely on the boot loader to change timer IRQs to active-low for us for 61 * now. 62 */ 63 gic: interrupt-controller@f2000000 { 64 compatible = "arm,gic-v3"; 65 interrupt-controller; 66 #interrupt-cells = <3>; 67 #address-cells = <1>; 68 #size-cells = <1>; 69 reg = <0xf2000000 0x10000>, 70 <0xf2040000 0x20000>; 71 }; 72 73 uart0: serial@131000 { 74 compatible = "arm,pl011", "arm,primecell"; 75 arm,primecell-periphid = <0x0018c011>; 76 reg = <0x00131000 0x1000>; 77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&uartclk>, <&uartclk>; 79 clock-names = "uartclk", "apb_pclk"; 80 status = "disabled"; 81 }; 82 83 uart1: serial@1408000 { 84 compatible = "arm,pl011", "arm,primecell"; 85 arm,primecell-periphid = <0x0018c011>; 86 reg = <0x01408000 0x1000>; 87 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 88 clocks = <&uartclk>, <&uartclk>; 89 clock-names = "uartclk", "apb_pclk"; 90 status = "disabled"; 91 }; 92 93 uart2: serial@140d000 { 94 compatible = "arm,pl011", "arm,primecell"; 95 arm,primecell-periphid = <0x0018c011>; 96 reg = <0x0140d000 0x1000>; 97 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&uartclk>, <&uartclk>; 99 clock-names = "uartclk", "apb_pclk"; 100 status = "disabled"; 101 }; 102 }; 103}; 104