1/* 2 * pdu001.dts 3 * 4 * EETS GmbH PDU001 board device tree file 5 * 6 * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/ 7 * 8 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13/dts-v1/; 14 15#include "am33xx.dtsi" 16#include <dt-bindings/interrupt-controller/irq.h> 17#include <dt-bindings/leds/leds-pca9532.h> 18 19/ { 20 model = "EETS,PDU001"; 21 compatible = "ti,am33xx"; 22 23 chosen { 24 stdout-path = &uart3; 25 }; 26 27 cpus { 28 cpu@0 { 29 cpu0-supply = <&vdd1_reg>; 30 }; 31 }; 32 33 memory { 34 device_type = "memory"; 35 reg = <0x80000000 0x10000000>; /* 256 MB */ 36 }; 37 38 vbat: fixedregulator@0 { 39 compatible = "regulator-fixed"; 40 regulator-name = "vbat"; 41 regulator-min-microvolt = <3600000>; 42 regulator-max-microvolt = <3600000>; 43 regulator-boot-on; 44 }; 45 46 lis3_reg: fixedregulator@1 { 47 compatible = "regulator-fixed"; 48 regulator-name = "lis3_reg"; 49 regulator-boot-on; 50 }; 51 52 panel { 53 compatible = "ti,tilcdc,panel"; 54 status = "okay"; 55 pinctrl-names = "default"; 56 pinctrl-0 = <&lcd_pins_s0>; 57 panel-info { 58 ac-bias = <255>; 59 ac-bias-intrpt = <0>; 60 dma-burst-sz = <16>; 61 bpp = <16>; 62 fdd = <0x80>; 63 sync-edge = <0>; 64 sync-ctrl = <1>; 65 raster-order = <0>; 66 fifo-th = <0>; 67 }; 68 69 display-timings { 70 timing-240x320p16 { 71 clock-frequency = <6500000>; 72 hactive = <240>; 73 vactive = <320>; 74 hfront-porch = <6>; 75 hback-porch = <6>; 76 hsync-len = <1>; 77 vback-porch = <6>; 78 vfront-porch = <6>; 79 vsync-len = <1>; 80 hsync-active = <0>; 81 vsync-active = <0>; 82 pixelclk-active = <1>; 83 de-active = <0>; 84 }; 85 }; 86 }; 87}; 88 89&am33xx_pinmux { 90 pinctrl-names = "default"; 91 pinctrl-0 = <&clkout2_pin>; 92 93 i2c0_pins: i2c0-pins { 94 pinctrl-single,pins = < 95 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) 96 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) 97 >; 98 }; 99 100 i2c1_pins: i2c1-pins { 101 pinctrl-single,pins = < 102 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ 103 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ 104 >; 105 }; 106 107 i2c2_pins: i2c2-pins { 108 pinctrl-single,pins = < 109 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_clk.i2c2_sda */ 110 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */ 111 >; 112 }; 113 114 spi1_pins: spi1-pins { 115 pinctrl-single,pins = < 116 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ 117 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ 118 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ 119 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ 120 >; 121 }; 122 123 uart0_pins: uart0-pins { 124 pinctrl-single,pins = < 125 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7) 126 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 127 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 128 >; 129 }; 130 131 uart1_pins: uart1-pins { 132 pinctrl-single,pins = < 133 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 134 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 135 >; 136 }; 137 138 uart3_pins: uart3-pins { 139 pinctrl-single,pins = < 140 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) /* spi0_cs1.uart3_rxd */ 141 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ 142 >; 143 }; 144 145 clkout2_pin: clkout2-pins { 146 pinctrl-single,pins = < 147 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ 148 >; 149 }; 150 151 cpsw_default: cpsw-default-pins { 152 pinctrl-single,pins = < 153 /* Port 1 (emac0) */ 154 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0) 155 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0) 156 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0) 157 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0) 158 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0) 159 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0) 160 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0) 161 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0) 162 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0) 163 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0) 164 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0) 165 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0) 166 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0) 167 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0) 168 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0) 169 170 /* Port 2 (emac1) */ 171 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* mii2_txen.gpmc_a0 */ 172 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1) /* mii2_rxdv.gpmc_a1 */ 173 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* mii2_txd3.gpmc_a2 */ 174 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* mii2_txd2.gpmc_a3 */ 175 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* mii2_txd1.gpmc_a4 */ 176 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* mii2_txd0.gpmc_a5 */ 177 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1) /* mii2_txclk.gpmc_a6 */ 178 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1) /* mii2_rxclk.gpmc_a7 */ 179 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1) /* mii2_rxd3.gpmc_a8 */ 180 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1) /* mii2_rxd2.gpmc_a9 */ 181 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1) /* mii2_rxd1.gpmc_a10 */ 182 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1) /* mii2_rxd0.gpmc_a11 */ 183 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1) /* mii2_crs.gpmc_wait0 */ 184 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1) /* mii2_rxer.gpmc_wpn */ 185 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1) /* mii2_col.gpmc_ben1 */ 186 >; 187 }; 188 189 davinci_mdio_default: davinci-mdio-default-pins { 190 pinctrl-single,pins = < 191 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 192 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 193 >; 194 }; 195 196 mmc1_pins: mmc1-pins { 197 /* eMMC */ 198 pinctrl-single,pins = < 199 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) 200 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) 201 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) 202 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) 203 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 204 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) 205 >; 206 }; 207 208 mmc2_pins: mmc2-pins { 209 /* SD cardcage */ 210 pinctrl-single,pins = < 211 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ 212 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ 213 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ 214 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ 215 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ 216 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ 217 /* card change signal for frontpanel SD cardcage */ 218 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ 219 >; 220 }; 221 222 lcd_pins_s0: lcd-s0-pins { 223 pinctrl-single,pins = < 224 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) 225 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) 226 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) 227 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) 228 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) 229 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) 230 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) 231 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) 232 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) 233 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) 234 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) 235 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) 236 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) 237 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) 238 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) 239 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) 240 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) 241 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) 242 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) 243 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) 244 >; 245 }; 246 247 dcan0_pins: dcan0-pins { 248 pinctrl-single,pins = < 249 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_ctsn.d_can0_tx */ 250 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart1_rtsn.d_can0_rx */ 251 >; 252 }; 253}; 254 255&uart0 { 256 pinctrl-names = "default"; 257 pinctrl-0 = <&uart0_pins>; 258 259 rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 260 rs485-rts-active-high; 261 rs485-rx-during-tx; 262 rs485-rts-delay = <0 0>; 263 linux,rs485-enabled-at-boot-time; 264 265 status = "okay"; 266}; 267 268&uart1 { 269 pinctrl-names = "default"; 270 pinctrl-0 = <&uart1_pins>; 271 272 status = "okay"; 273}; 274 275&uart3 { 276 pinctrl-names = "default"; 277 pinctrl-0 = <&uart3_pins>; 278 279 status = "okay"; 280}; 281 282&i2c0 { 283 pinctrl-names = "default"; 284 pinctrl-0 = <&i2c0_pins>; 285 286 status = "okay"; 287 clock-frequency = <400000>; 288 289 tps: tps@2d { 290 reg = <0x2d>; 291 }; 292 293 m2_eeprom: eeprom@50 { 294 compatible = "atmel,24c256"; 295 reg = <0x50>; 296 status = "okay"; 297 }; 298}; 299 300&i2c1 { 301 pinctrl-names = "default"; 302 pinctrl-0 = <&i2c1_pins>; 303 304 status = "okay"; 305 clock-frequency = <100000>; 306 307 board_24aa025e48: eeprom@50 { 308 compatible = "atmel,24c02"; 309 reg = <0x50>; 310 }; 311 312 backplane_24aa025e48: eeprom@53 { 313 compatible = "atmel,24c02"; 314 reg = <0x53>; 315 }; 316 317 pca9532: pca9532@60 { 318 compatible = "nxp,pca9532"; 319 reg = <0x60>; 320 psc0 = <0x97>; 321 pwm0 = <0x80>; 322 psc1 = <0x97>; 323 pwm1 = <0x10>; 324 325 run.red@0 { 326 type = <PCA9532_TYPE_LED>; 327 }; 328 run.green@1 { 329 type = <PCA9532_TYPE_LED>; 330 default-state = "on"; 331 }; 332 s2.red@2 { 333 type = <PCA9532_TYPE_LED>; 334 }; 335 s2.green@3 { 336 type = <PCA9532_TYPE_LED>; 337 }; 338 s1.yellow@4 { 339 type = <PCA9532_TYPE_LED>; 340 }; 341 s1.green@5 { 342 type = <PCA9532_TYPE_LED>; 343 }; 344 }; 345 346 pca9530: pca9530@61 { 347 compatible = "nxp,pca9530"; 348 reg = <0x61>; 349 350 tft-panel@0 { 351 type = <PCA9532_TYPE_LED>; 352 linux,default-trigger = "backlight"; 353 default-state = "on"; 354 }; 355 }; 356 357 mcp79400: rtc@6f { 358 compatible = "microchip,mcp7940x"; 359 reg = <0x6f>; 360 }; 361}; 362 363&i2c2 { 364 pinctrl-names = "default"; 365 pinctrl-0 = <&i2c2_pins>; 366 367 status = "okay"; 368 clock-frequency = <100000>; 369}; 370 371&spi1 { 372 pinctrl-names = "default"; 373 pinctrl-0 = <&spi1_pins>; 374 ti,pindir-d0-out-d1-in; 375 status = "okay"; 376 377 display-controller@0 { 378 compatible = "orisetech,otm3225a"; 379 reg = <0>; 380 spi-max-frequency = <1000000>; 381 // SPI mode 3 382 spi-cpol; 383 spi-cpha; 384 status = "okay"; 385 }; 386}; 387 388/* 389 * Disable soc's rtc as we have no VBAT for it. This makes the board 390 * rtc (Microchip MCP79400) the default rtc device 'rtc0'. 391 */ 392&rtc { 393 status = "disabled"; 394}; 395 396&lcdc { 397 status = "okay"; 398}; 399 400&elm { 401 status = "okay"; 402}; 403 404#include "../../tps65910.dtsi" 405 406&tps { 407 vcc1-supply = <&vbat>; 408 vcc2-supply = <&vbat>; 409 vcc3-supply = <&vbat>; 410 vcc4-supply = <&vbat>; 411 vcc5-supply = <&vbat>; 412 vcc6-supply = <&vbat>; 413 vcc7-supply = <&vbat>; 414 vccio-supply = <&vbat>; 415 416 regulators { 417 vrtc_reg: regulator@0 { 418 regulator-name = "ldo_vrtc"; 419 regulator-always-on; 420 }; 421 422 vio_reg: regulator@1 { 423 regulator-name = "buck_vdd_ddr"; 424 regulator-always-on; 425 }; 426 427 vdd1_reg: regulator@2 { 428 /* VDD_MPU voltage limits */ 429 regulator-name = "buck_vdd_mpu"; 430 regulator-min-microvolt = <912500>; 431 regulator-max-microvolt = <1312500>; 432 regulator-boot-on; 433 regulator-always-on; 434 }; 435 436 vdd2_reg: regulator@3 { 437 /* VDD_CORE voltage limits */ 438 regulator-name = "buck_vdd_core"; 439 regulator-min-microvolt = <912500>; 440 regulator-max-microvolt = <1150000>; 441 regulator-boot-on; 442 regulator-always-on; 443 }; 444 445 vdd3_reg: regulator@4 { 446 regulator-name = "boost_res"; 447 regulator-always-on; 448 }; 449 450 vdig1_reg: regulator@5 { 451 regulator-name = "ldo_vdig1"; 452 regulator-always-on; 453 }; 454 455 vdig2_reg: regulator@6 { 456 regulator-name = "ldo_vdig2"; 457 regulator-always-on; 458 }; 459 460 vpll_reg: regulator@7 { 461 regulator-name = "ldo_vpll"; 462 regulator-always-on; 463 }; 464 465 vdac_reg: regulator@8 { 466 regulator-name = "ldo_vdac"; 467 regulator-always-on; 468 }; 469 470 vaux1_reg: regulator@9 { 471 regulator-name = "ldo_vaux1"; 472 regulator-always-on; 473 }; 474 475 vaux2_reg: regulator@10 { 476 regulator-name = "ldo_vaux2"; 477 regulator-always-on; 478 }; 479 480 vaux33_reg: regulator@11 { 481 regulator-name = "ldo_vaux33"; 482 regulator-always-on; 483 }; 484 485 vmmc_reg: regulator@12 { 486 regulator-name = "ldo_vmmc"; 487 regulator-min-microvolt = <1800000>; 488 regulator-max-microvolt = <3300000>; 489 regulator-always-on; 490 }; 491 492 vbb_reg: regulator@13 { 493 regulator-name = "bat_vbb"; 494 }; 495 }; 496}; 497 498&mac_sw { 499 pinctrl-names = "default"; 500 pinctrl-0 = <&cpsw_default>; 501 status = "okay"; 502}; 503 504&davinci_mdio_sw { 505 pinctrl-names = "default"; 506 pinctrl-0 = <&davinci_mdio_default>; 507 508 ethphy0: ethernet-phy@0 { 509 reg = <0>; 510 }; 511 512 ethphy1: ethernet-phy@1 { 513 reg = <1>; 514 }; 515}; 516 517&cpsw_port1 { 518 phy-handle = <ðphy0>; 519 phy-mode = "mii"; 520 ti,dual-emac-pvid = <1>; 521}; 522 523&cpsw_port2 { 524 phy-handle = <ðphy1>; 525 phy-mode = "mii"; 526 ti,dual-emac-pvid = <2>; 527}; 528 529&tscadc { 530 status = "okay"; 531 tsc { 532 ti,wires = <4>; 533 ti,x-plate-resistance = <200>; 534 ti,coordinate-readouts = <5>; 535 ti,wire-config = <0x01 0x10 0x22 0x33>; 536 ti,charge-delay = <0x400>; 537 }; 538 539 adc { 540 ti,adc-channels = <4 5 6 7>; 541 }; 542}; 543 544&mmc1 { 545 status = "okay"; 546 vmmc-supply = <&vmmc_reg>; 547 bus-width = <4>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&mmc1_pins>; 550 non-removable; 551}; 552 553&mmc2 { 554 status = "okay"; 555 vmmc-supply = <&vmmc_reg>; 556 bus-width = <4>; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&mmc2_pins>; 559 cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; 560}; 561 562&sham { 563 status = "okay"; 564}; 565 566&aes { 567 status = "okay"; 568}; 569 570&dcan0 { 571 status = "okay"; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&dcan0_pins>; 574}; 575