1// SPDX-License-Identifier: GPL-2.0 2/* 3 * DT overlay for IDK AM335x 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8/* 9 * AM335x ICE V2 board 10 * http://www.ti.com/tool/tmdsice3359 11 */ 12 13/dts-v1/; 14/plugin/; 15 16#include <dt-bindings/bus/ti-sysc.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/pinctrl/am33xx.h> 19#include <dt-bindings/clock/am3.h> 20 21&{/} { 22 /* Dual-MAC Ethernet application node on PRU-ICSS */ 23 pruss_eth: pruss-eth { 24 compatible = "ti,am3359-prueth"; 25 ti,prus = <&pru0>, <&pru1>; 26 sram = <&ocmcram>; 27 ti,mii-rt = <&pruss_mii_rt>; 28 ti,iep = <&pruss_iep>; 29 ti,ecap = <&pruss_ecap>; 30 interrupts = <20 2 2>, <21 3 3>; 31 interrupt-names = "rx_hp", "rx_lp"; 32 interrupt-parent = <&pruss_intc>; 33 34 pinctrl-0 = <&pruss_eth_default>; 35 pinctrl-names = "default"; 36 37 ethernet-ports { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 pruss_emac0: ethernet-port@0 { 41 reg = <0>; 42 phy-handle = <&pruss_eth0_phy>; 43 phy-mode = "mii"; 44 interrupts = <20 2 2>, <26 6 6>, <23 6 6>; 45 interrupt-names = "rx", "emac_ptp_tx", 46 "hsr_ptp_tx"; 47 /* Filled in by bootloader */ 48 local-mac-address = [00 00 00 00 00 00]; 49 }; 50 51 pruss_emac1: ethernet-port@1 { 52 reg = <1>; 53 phy-handle = <&pruss_eth1_phy>; 54 phy-mode = "mii"; 55 interrupts = <21 3 3>, <27 9 7>, <24 9 7>; 56 interrupt-names = "rx", "emac_ptp_tx", 57 "hsr_ptp_tx"; 58 /* Filled in by bootloader */ 59 local-mac-address = [00 00 00 00 00 00]; 60 }; 61 }; 62 }; 63}; 64 65&am33xx_pinmux { 66 /* MDIO node for PRU-ICSS */ 67 pruss_mdio_default: pruss-mdio-default-pins { 68 pinctrl-single,pins = < 69 AM33XX_IOPAD(0x88c, PIN_OUTPUT | MUX_MODE5) /* (V12) gpmc_clk.pr1_mdio_mdclk */ 70 AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE5) /* (T13) gpmc_csn3.pr1_mdio_data */ 71 >; 72 }; 73 74 /* Pinmux configuration for PRU-ICSS */ 75 pruss_eth_default: pruss-eth-default-pins { 76 pinctrl-single,pins = < 77 AM33XX_IOPAD(0x8a0, PIN_INPUT | MUX_MODE2) /* (R1) lcd_data0.pr1_mii_mt0_clk */ 78 AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE2) /* (T2) lcd_data5.pr1_mii0_txd0 */ 79 AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE2) /* (T1) lcd_data4.pr1_mii0_txd1 */ 80 AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE2) /* (R4) lcd_data3.pr1_mii0_txd2 */ 81 AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE2) /* (R3) lcd_data2.pr1_mii0_txd3 */ 82 AM33XX_IOPAD(0x8cc, PIN_INPUT | MUX_MODE5) /* (U4) lcd_data11.pr1_mii0_rxd0 */ 83 AM33XX_IOPAD(0x8c8, PIN_INPUT | MUX_MODE5) /* (U3) lcd_data10.pr1_mii0_rxd1 */ 84 AM33XX_IOPAD(0x8c4, PIN_INPUT | MUX_MODE5) /* (U2) lcd_data9.pr1_mii0_rxd2 */ 85 AM33XX_IOPAD(0x8c0, PIN_INPUT | MUX_MODE5) /* (U1) lcd_data8.pr1_mii0_rxd3 */ 86 AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE2) /* (R2) lcd_data1.pr1_mii0_txen */ 87 AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE5) /* (V4) lcd_data14.pr1_mii_mr0_clk */ 88 AM33XX_IOPAD(0x8dc, PIN_INPUT | MUX_MODE5) /* (T5) lcd_data15.pr1_mii0_rxdv */ 89 AM33XX_IOPAD(0x8d4, PIN_INPUT | MUX_MODE5) /* (V3) lcd_data13.pr1_mii0_rxer */ 90 AM33XX_IOPAD(0x8d0, PIN_INPUT | MUX_MODE5) /* (V2) lcd_data12.pr1_mii0_rxlink */ 91 AM33XX_IOPAD(0x8e8, PIN_INPUT | MUX_MODE2) /* (V5) lcd_pclk.pr1_mii0_crs */ 92 93 AM33XX_IOPAD(0x840, PIN_INPUT | MUX_MODE5) /* (R13) gpmc_a0.pr1_mii_mt1_clk */ 94 AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE5) /* (R14) gpmc_a4.pr1_mii1_txd0 */ 95 AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE5) /* (T14) gpmc_a3.pr1_mii1_txd1 */ 96 AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE5) /* (U14) gpmc_a2.pr1_mii1_txd2 */ 97 AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE5) /* (V14) gpmc_a1.pr1_mii1_txd3 */ 98 AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE5) /* (V16) gpmc_a8.pr1_mii1_rxd0 */ 99 AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE5) /* (T15) gpmc_a7.pr1_mii1_rxd1 */ 100 AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE5) /* (U15) gpmc_a6.pr1_mii1_rxd2 */ 101 AM33XX_IOPAD(0x854, PIN_INPUT | MUX_MODE5) /* (V15) gpmc_a5.pr1_mii1_rxd3 */ 102 AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE5) /* (U17) gpmc_wpn.pr1_mii1_txen */ 103 AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE5) /* (U16) gpmc_a9.pr1_mii_mr1_clk */ 104 AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE5) /* (T16) gpmc_a10.pr1_mii1_rxdv */ 105 AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE5) /* (V17) gpmc_a11.pr1_mii1_rxer */ 106 AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE5) /* (U18) gpmc_be1n.pr1_mii1_rxlink */ 107 AM33XX_IOPAD(0x8ec, PIN_INPUT | MUX_MODE2) /* (R6) lcd_ac_bias_en.pr1_mii1_crs */ 108 >; 109 }; 110}; 111 112&gpio3 { 113 mux-mii-hog { 114 status = "disabled"; 115 }; 116 117 mux-mii-hog-0 { 118 gpio-hog; 119 gpios = <10 GPIO_ACTIVE_HIGH>; 120 /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ 121 output-low; 122 line-name = "MUX_MII_CTL1"; 123 }; 124}; 125 126/* 127 * Disable CPSW switch node and 128 * MDIO configuration to prevent 129 * conflict with PRU-ICSS 130 */ 131&mac_sw { 132 status = "disabled"; 133}; 134 135&davinci_mdio_sw { 136 status = "disabled"; 137}; 138 139/* PRU-ICSS MDIO configuration */ 140&pruss_mdio { 141 pinctrl-0 = <&pruss_mdio_default>; 142 pinctrl-names = "default"; 143 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; 144 reset-delay-us = <2>; /* PHY datasheet states 1uS min */ 145 status = "okay"; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 149 pruss_eth0_phy: ethernet-phy@1 { 150 reg = <1>; 151 }; 152 153 pruss_eth1_phy: ethernet-phy@3 { 154 reg = <3>; 155 }; 156}; 157