1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/reset/stm32mp13-resets.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 device_type = "cpu"; 21 reg = <0>; 22 }; 23 }; 24 25 arm-pmu { 26 compatible = "arm,cortex-a7-pmu"; 27 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 28 interrupt-affinity = <&cpu0>; 29 interrupt-parent = <&intc>; 30 }; 31 32 firmware { 33 optee { 34 method = "smc"; 35 compatible = "linaro,optee-tz"; 36 interrupt-parent = <&intc>; 37 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 38 }; 39 40 scmi: scmi { 41 compatible = "linaro,scmi-optee"; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 linaro,optee-channel-id = <0>; 45 46 scmi_clk: protocol@14 { 47 reg = <0x14>; 48 #clock-cells = <1>; 49 }; 50 51 scmi_reset: protocol@16 { 52 reg = <0x16>; 53 #reset-cells = <1>; 54 }; 55 56 scmi_voltd: protocol@17 { 57 reg = <0x17>; 58 59 scmi_regu: regulators { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 scmi_reg11: regulator@0 { 64 reg = <VOLTD_SCMI_REG11>; 65 regulator-name = "reg11"; 66 }; 67 scmi_reg18: regulator@1 { 68 reg = <VOLTD_SCMI_REG18>; 69 regulator-name = "reg18"; 70 }; 71 scmi_usb33: regulator@2 { 72 reg = <VOLTD_SCMI_USB33>; 73 regulator-name = "usb33"; 74 }; 75 }; 76 }; 77 }; 78 }; 79 80 intc: interrupt-controller@a0021000 { 81 compatible = "arm,cortex-a7-gic"; 82 #interrupt-cells = <3>; 83 interrupt-controller; 84 reg = <0xa0021000 0x1000>, 85 <0xa0022000 0x2000>; 86 }; 87 88 psci { 89 compatible = "arm,psci-1.0"; 90 method = "smc"; 91 }; 92 93 timer { 94 compatible = "arm,armv7-timer"; 95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 96 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 98 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 99 interrupt-parent = <&intc>; 100 always-on; 101 }; 102 103 soc { 104 compatible = "simple-bus"; 105 #address-cells = <1>; 106 #size-cells = <1>; 107 interrupt-parent = <&intc>; 108 ranges; 109 110 timers2: timer@40000000 { 111 #address-cells = <1>; 112 #size-cells = <0>; 113 compatible = "st,stm32-timers"; 114 reg = <0x40000000 0x400>; 115 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-names = "global"; 117 clocks = <&rcc TIM2_K>; 118 clock-names = "int"; 119 dmas = <&dmamux1 18 0x400 0x1>, 120 <&dmamux1 19 0x400 0x1>, 121 <&dmamux1 20 0x400 0x1>, 122 <&dmamux1 21 0x400 0x1>, 123 <&dmamux1 22 0x400 0x1>; 124 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 125 status = "disabled"; 126 127 pwm { 128 compatible = "st,stm32-pwm"; 129 #pwm-cells = <3>; 130 status = "disabled"; 131 }; 132 133 timer@1 { 134 compatible = "st,stm32h7-timer-trigger"; 135 reg = <1>; 136 status = "disabled"; 137 }; 138 139 counter { 140 compatible = "st,stm32-timer-counter"; 141 status = "disabled"; 142 }; 143 }; 144 145 timers3: timer@40001000 { 146 #address-cells = <1>; 147 #size-cells = <0>; 148 compatible = "st,stm32-timers"; 149 reg = <0x40001000 0x400>; 150 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-names = "global"; 152 clocks = <&rcc TIM3_K>; 153 clock-names = "int"; 154 dmas = <&dmamux1 23 0x400 0x1>, 155 <&dmamux1 24 0x400 0x1>, 156 <&dmamux1 25 0x400 0x1>, 157 <&dmamux1 26 0x400 0x1>, 158 <&dmamux1 27 0x400 0x1>, 159 <&dmamux1 28 0x400 0x1>; 160 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 161 status = "disabled"; 162 163 pwm { 164 compatible = "st,stm32-pwm"; 165 #pwm-cells = <3>; 166 status = "disabled"; 167 }; 168 169 timer@2 { 170 compatible = "st,stm32h7-timer-trigger"; 171 reg = <2>; 172 status = "disabled"; 173 }; 174 175 counter { 176 compatible = "st,stm32-timer-counter"; 177 status = "disabled"; 178 }; 179 }; 180 181 timers4: timer@40002000 { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 compatible = "st,stm32-timers"; 185 reg = <0x40002000 0x400>; 186 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 187 interrupt-names = "global"; 188 clocks = <&rcc TIM4_K>; 189 clock-names = "int"; 190 dmas = <&dmamux1 29 0x400 0x1>, 191 <&dmamux1 30 0x400 0x1>, 192 <&dmamux1 31 0x400 0x1>, 193 <&dmamux1 32 0x400 0x1>; 194 dma-names = "ch1", "ch2", "ch3", "up"; 195 status = "disabled"; 196 197 pwm { 198 compatible = "st,stm32-pwm"; 199 #pwm-cells = <3>; 200 status = "disabled"; 201 }; 202 203 timer@3 { 204 compatible = "st,stm32h7-timer-trigger"; 205 reg = <3>; 206 status = "disabled"; 207 }; 208 209 counter { 210 compatible = "st,stm32-timer-counter"; 211 status = "disabled"; 212 }; 213 }; 214 215 timers5: timer@40003000 { 216 #address-cells = <1>; 217 #size-cells = <0>; 218 compatible = "st,stm32-timers"; 219 reg = <0x40003000 0x400>; 220 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 221 interrupt-names = "global"; 222 clocks = <&rcc TIM5_K>; 223 clock-names = "int"; 224 dmas = <&dmamux1 55 0x400 0x1>, 225 <&dmamux1 56 0x400 0x1>, 226 <&dmamux1 57 0x400 0x1>, 227 <&dmamux1 58 0x400 0x1>, 228 <&dmamux1 59 0x400 0x1>, 229 <&dmamux1 60 0x400 0x1>; 230 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 231 status = "disabled"; 232 233 pwm { 234 compatible = "st,stm32-pwm"; 235 #pwm-cells = <3>; 236 status = "disabled"; 237 }; 238 239 timer@4 { 240 compatible = "st,stm32h7-timer-trigger"; 241 reg = <4>; 242 status = "disabled"; 243 }; 244 245 counter { 246 compatible = "st,stm32-timer-counter"; 247 status = "disabled"; 248 }; 249 }; 250 251 timers6: timer@40004000 { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 compatible = "st,stm32-timers"; 255 reg = <0x40004000 0x400>; 256 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 257 interrupt-names = "global"; 258 clocks = <&rcc TIM6_K>; 259 clock-names = "int"; 260 dmas = <&dmamux1 69 0x400 0x1>; 261 dma-names = "up"; 262 status = "disabled"; 263 264 counter { 265 compatible = "st,stm32-timer-counter"; 266 status = "disabled"; 267 }; 268 269 timer@5 { 270 compatible = "st,stm32h7-timer-trigger"; 271 reg = <5>; 272 status = "disabled"; 273 }; 274 }; 275 276 timers7: timer@40005000 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 compatible = "st,stm32-timers"; 280 reg = <0x40005000 0x400>; 281 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 282 interrupt-names = "global"; 283 clocks = <&rcc TIM7_K>; 284 clock-names = "int"; 285 dmas = <&dmamux1 70 0x400 0x1>; 286 dma-names = "up"; 287 status = "disabled"; 288 289 counter { 290 compatible = "st,stm32-timer-counter"; 291 status = "disabled"; 292 }; 293 294 timer@6 { 295 compatible = "st,stm32h7-timer-trigger"; 296 reg = <6>; 297 status = "disabled"; 298 }; 299 }; 300 301 lptimer1: timer@40009000 { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 compatible = "st,stm32-lptimer"; 305 reg = <0x40009000 0x400>; 306 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&rcc LPTIM1_K>; 308 clock-names = "mux"; 309 wakeup-source; 310 status = "disabled"; 311 312 pwm { 313 compatible = "st,stm32-pwm-lp"; 314 #pwm-cells = <3>; 315 status = "disabled"; 316 }; 317 318 trigger@0 { 319 compatible = "st,stm32-lptimer-trigger"; 320 reg = <0>; 321 status = "disabled"; 322 }; 323 324 counter { 325 compatible = "st,stm32-lptimer-counter"; 326 status = "disabled"; 327 }; 328 329 timer { 330 compatible = "st,stm32-lptimer-timer"; 331 status = "disabled"; 332 }; 333 }; 334 335 i2s2: audio-controller@4000b000 { 336 compatible = "st,stm32h7-i2s"; 337 reg = <0x4000b000 0x400>; 338 #sound-dai-cells = <0>; 339 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 340 dmas = <&dmamux1 39 0x400 0x01>, 341 <&dmamux1 40 0x400 0x01>; 342 dma-names = "rx", "tx"; 343 status = "disabled"; 344 }; 345 346 spi2: spi@4000b000 { 347 compatible = "st,stm32h7-spi"; 348 reg = <0x4000b000 0x400>; 349 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&rcc SPI2_K>; 351 resets = <&rcc SPI2_R>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 dmas = <&dmamux1 39 0x400 0x01>, 355 <&dmamux1 40 0x400 0x01>; 356 dma-names = "rx", "tx"; 357 status = "disabled"; 358 }; 359 360 i2s3: audio-controller@4000c000 { 361 compatible = "st,stm32h7-i2s"; 362 reg = <0x4000c000 0x400>; 363 #sound-dai-cells = <0>; 364 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 365 dmas = <&dmamux1 61 0x400 0x01>, 366 <&dmamux1 62 0x400 0x01>; 367 dma-names = "rx", "tx"; 368 status = "disabled"; 369 }; 370 371 spi3: spi@4000c000 { 372 compatible = "st,stm32h7-spi"; 373 reg = <0x4000c000 0x400>; 374 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&rcc SPI3_K>; 376 resets = <&rcc SPI3_R>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 dmas = <&dmamux1 61 0x400 0x01>, 380 <&dmamux1 62 0x400 0x01>; 381 dma-names = "rx", "tx"; 382 status = "disabled"; 383 }; 384 385 spdifrx: audio-controller@4000d000 { 386 compatible = "st,stm32h7-spdifrx"; 387 reg = <0x4000d000 0x400>; 388 #sound-dai-cells = <0>; 389 clocks = <&rcc SPDIF_K>; 390 clock-names = "kclk"; 391 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 392 dmas = <&dmamux1 93 0x400 0x01>, 393 <&dmamux1 94 0x400 0x01>; 394 dma-names = "rx", "rx-ctrl"; 395 status = "disabled"; 396 }; 397 398 usart3: serial@4000f000 { 399 compatible = "st,stm32h7-uart"; 400 reg = <0x4000f000 0x400>; 401 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&rcc USART3_K>; 403 resets = <&rcc USART3_R>; 404 wakeup-source; 405 dmas = <&dmamux1 45 0x400 0x5>, 406 <&dmamux1 46 0x400 0x1>; 407 dma-names = "rx", "tx"; 408 status = "disabled"; 409 }; 410 411 uart4: serial@40010000 { 412 compatible = "st,stm32h7-uart"; 413 reg = <0x40010000 0x400>; 414 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&rcc UART4_K>; 416 resets = <&rcc UART4_R>; 417 wakeup-source; 418 dmas = <&dmamux1 63 0x400 0x5>, 419 <&dmamux1 64 0x400 0x1>; 420 dma-names = "rx", "tx"; 421 status = "disabled"; 422 }; 423 424 uart5: serial@40011000 { 425 compatible = "st,stm32h7-uart"; 426 reg = <0x40011000 0x400>; 427 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&rcc UART5_K>; 429 resets = <&rcc UART5_R>; 430 wakeup-source; 431 dmas = <&dmamux1 65 0x400 0x5>, 432 <&dmamux1 66 0x400 0x1>; 433 dma-names = "rx", "tx"; 434 status = "disabled"; 435 }; 436 437 i2c1: i2c@40012000 { 438 compatible = "st,stm32mp13-i2c"; 439 reg = <0x40012000 0x400>; 440 interrupt-names = "event", "error"; 441 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&rcc I2C1_K>; 444 resets = <&rcc I2C1_R>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 dmas = <&dmamux1 33 0x400 0x1>, 448 <&dmamux1 34 0x400 0x1>; 449 dma-names = "rx", "tx"; 450 st,syscfg-fmp = <&syscfg 0x4 0x1>; 451 i2c-analog-filter; 452 status = "disabled"; 453 }; 454 455 i2c2: i2c@40013000 { 456 compatible = "st,stm32mp13-i2c"; 457 reg = <0x40013000 0x400>; 458 interrupt-names = "event", "error"; 459 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&rcc I2C2_K>; 462 resets = <&rcc I2C2_R>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 dmas = <&dmamux1 35 0x400 0x1>, 466 <&dmamux1 36 0x400 0x1>; 467 dma-names = "rx", "tx"; 468 st,syscfg-fmp = <&syscfg 0x4 0x2>; 469 i2c-analog-filter; 470 status = "disabled"; 471 }; 472 473 uart7: serial@40018000 { 474 compatible = "st,stm32h7-uart"; 475 reg = <0x40018000 0x400>; 476 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&rcc UART7_K>; 478 resets = <&rcc UART7_R>; 479 wakeup-source; 480 dmas = <&dmamux1 79 0x400 0x5>, 481 <&dmamux1 80 0x400 0x1>; 482 dma-names = "rx", "tx"; 483 status = "disabled"; 484 }; 485 486 uart8: serial@40019000 { 487 compatible = "st,stm32h7-uart"; 488 reg = <0x40019000 0x400>; 489 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&rcc UART8_K>; 491 resets = <&rcc UART8_R>; 492 wakeup-source; 493 dmas = <&dmamux1 81 0x400 0x5>, 494 <&dmamux1 82 0x400 0x1>; 495 dma-names = "rx", "tx"; 496 status = "disabled"; 497 }; 498 499 timers1: timer@44000000 { 500 #address-cells = <1>; 501 #size-cells = <0>; 502 compatible = "st,stm32-timers"; 503 reg = <0x44000000 0x400>; 504 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 508 interrupt-names = "brk", "up", "trg-com", "cc"; 509 clocks = <&rcc TIM1_K>; 510 clock-names = "int"; 511 dmas = <&dmamux1 11 0x400 0x1>, 512 <&dmamux1 12 0x400 0x1>, 513 <&dmamux1 13 0x400 0x1>, 514 <&dmamux1 14 0x400 0x1>, 515 <&dmamux1 15 0x400 0x1>, 516 <&dmamux1 16 0x400 0x1>, 517 <&dmamux1 17 0x400 0x1>; 518 dma-names = "ch1", "ch2", "ch3", "ch4", 519 "up", "trig", "com"; 520 status = "disabled"; 521 522 pwm { 523 compatible = "st,stm32-pwm"; 524 #pwm-cells = <3>; 525 status = "disabled"; 526 }; 527 528 timer@0 { 529 compatible = "st,stm32h7-timer-trigger"; 530 reg = <0>; 531 status = "disabled"; 532 }; 533 534 counter { 535 compatible = "st,stm32-timer-counter"; 536 status = "disabled"; 537 }; 538 }; 539 540 timers8: timer@44001000 { 541 #address-cells = <1>; 542 #size-cells = <0>; 543 compatible = "st,stm32-timers"; 544 reg = <0x44001000 0x400>; 545 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 549 interrupt-names = "brk", "up", "trg-com", "cc"; 550 clocks = <&rcc TIM8_K>; 551 clock-names = "int"; 552 dmas = <&dmamux1 47 0x400 0x1>, 553 <&dmamux1 48 0x400 0x1>, 554 <&dmamux1 49 0x400 0x1>, 555 <&dmamux1 50 0x400 0x1>, 556 <&dmamux1 51 0x400 0x1>, 557 <&dmamux1 52 0x400 0x1>, 558 <&dmamux1 53 0x400 0x1>; 559 dma-names = "ch1", "ch2", "ch3", "ch4", 560 "up", "trig", "com"; 561 status = "disabled"; 562 563 pwm { 564 compatible = "st,stm32-pwm"; 565 #pwm-cells = <3>; 566 status = "disabled"; 567 }; 568 569 timer@7 { 570 compatible = "st,stm32h7-timer-trigger"; 571 reg = <7>; 572 status = "disabled"; 573 }; 574 575 counter { 576 compatible = "st,stm32-timer-counter"; 577 status = "disabled"; 578 }; 579 }; 580 581 usart6: serial@44003000 { 582 compatible = "st,stm32h7-uart"; 583 reg = <0x44003000 0x400>; 584 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&rcc USART6_K>; 586 resets = <&rcc USART6_R>; 587 wakeup-source; 588 dmas = <&dmamux1 71 0x400 0x5>, 589 <&dmamux1 72 0x400 0x1>; 590 dma-names = "rx", "tx"; 591 status = "disabled"; 592 }; 593 594 i2s1: audio-controller@44004000 { 595 compatible = "st,stm32h7-i2s"; 596 reg = <0x44004000 0x400>; 597 #sound-dai-cells = <0>; 598 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 599 dmas = <&dmamux1 37 0x400 0x01>, 600 <&dmamux1 38 0x400 0x01>; 601 dma-names = "rx", "tx"; 602 status = "disabled"; 603 }; 604 605 spi1: spi@44004000 { 606 compatible = "st,stm32h7-spi"; 607 reg = <0x44004000 0x400>; 608 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&rcc SPI1_K>; 610 resets = <&rcc SPI1_R>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 dmas = <&dmamux1 37 0x400 0x01>, 614 <&dmamux1 38 0x400 0x01>; 615 dma-names = "rx", "tx"; 616 status = "disabled"; 617 }; 618 619 sai1: sai@4400a000 { 620 compatible = "st,stm32h7-sai"; 621 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 622 ranges = <0 0x4400a000 0x400>; 623 #address-cells = <1>; 624 #size-cells = <1>; 625 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 626 resets = <&rcc SAI1_R>; 627 status = "disabled"; 628 629 sai1a: audio-controller@4400a004 { 630 compatible = "st,stm32-sai-sub-a"; 631 reg = <0x4 0x20>; 632 #sound-dai-cells = <0>; 633 clocks = <&rcc SAI1_K>; 634 clock-names = "sai_ck"; 635 dmas = <&dmamux1 87 0x400 0x01>; 636 status = "disabled"; 637 }; 638 639 sai1b: audio-controller@4400a024 { 640 compatible = "st,stm32-sai-sub-b"; 641 reg = <0x24 0x20>; 642 #sound-dai-cells = <0>; 643 clocks = <&rcc SAI1_K>; 644 clock-names = "sai_ck"; 645 dmas = <&dmamux1 88 0x400 0x01>; 646 status = "disabled"; 647 }; 648 }; 649 650 sai2: sai@4400b000 { 651 compatible = "st,stm32h7-sai"; 652 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 653 ranges = <0 0x4400b000 0x400>; 654 #address-cells = <1>; 655 #size-cells = <1>; 656 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 657 resets = <&rcc SAI2_R>; 658 status = "disabled"; 659 660 sai2a: audio-controller@4400b004 { 661 compatible = "st,stm32-sai-sub-a"; 662 reg = <0x4 0x20>; 663 #sound-dai-cells = <0>; 664 clocks = <&rcc SAI2_K>; 665 clock-names = "sai_ck"; 666 dmas = <&dmamux1 89 0x400 0x01>; 667 status = "disabled"; 668 }; 669 670 sai2b: audio-controller@4400b024 { 671 compatible = "st,stm32-sai-sub-b"; 672 reg = <0x24 0x20>; 673 #sound-dai-cells = <0>; 674 clocks = <&rcc SAI2_K>; 675 clock-names = "sai_ck"; 676 dmas = <&dmamux1 90 0x400 0x01>; 677 status = "disabled"; 678 }; 679 }; 680 681 dfsdm: dfsdm@4400d000 { 682 compatible = "st,stm32mp1-dfsdm"; 683 reg = <0x4400d000 0x800>; 684 clocks = <&rcc DFSDM_K>; 685 clock-names = "dfsdm"; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 status = "disabled"; 689 690 dfsdm0: filter@0 { 691 compatible = "st,stm32-dfsdm-adc"; 692 reg = <0>; 693 #io-channel-cells = <1>; 694 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 695 dmas = <&dmamux1 101 0x400 0x01>; 696 dma-names = "rx"; 697 status = "disabled"; 698 }; 699 700 dfsdm1: filter@1 { 701 compatible = "st,stm32-dfsdm-adc"; 702 reg = <1>; 703 #io-channel-cells = <1>; 704 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 705 dmas = <&dmamux1 102 0x400 0x01>; 706 dma-names = "rx"; 707 status = "disabled"; 708 }; 709 }; 710 711 dma1: dma-controller@48000000 { 712 compatible = "st,stm32-dma"; 713 reg = <0x48000000 0x400>; 714 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&rcc DMA1>; 723 resets = <&rcc DMA1_R>; 724 #dma-cells = <4>; 725 st,mem2mem; 726 dma-requests = <8>; 727 }; 728 729 dma2: dma-controller@48001000 { 730 compatible = "st,stm32-dma"; 731 reg = <0x48001000 0x400>; 732 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&rcc DMA2>; 741 resets = <&rcc DMA2_R>; 742 #dma-cells = <4>; 743 st,mem2mem; 744 dma-requests = <8>; 745 }; 746 747 dmamux1: dma-router@48002000 { 748 compatible = "st,stm32h7-dmamux"; 749 reg = <0x48002000 0x40>; 750 clocks = <&rcc DMAMUX1>; 751 resets = <&rcc DMAMUX1_R>; 752 #dma-cells = <3>; 753 dma-masters = <&dma1 &dma2>; 754 dma-requests = <128>; 755 dma-channels = <16>; 756 }; 757 758 rcc: rcc@50000000 { 759 compatible = "st,stm32mp13-rcc", "syscon"; 760 reg = <0x50000000 0x1000>; 761 #clock-cells = <1>; 762 #reset-cells = <1>; 763 clock-names = "hse", "hsi", "csi", "lse", "lsi"; 764 clocks = <&scmi_clk CK_SCMI_HSE>, 765 <&scmi_clk CK_SCMI_HSI>, 766 <&scmi_clk CK_SCMI_CSI>, 767 <&scmi_clk CK_SCMI_LSE>, 768 <&scmi_clk CK_SCMI_LSI>; 769 }; 770 771 pwr_regulators: pwr@50001000 { 772 compatible = "st,stm32mp1,pwr-reg"; 773 reg = <0x50001000 0x10>; 774 status = "disabled"; 775 776 reg11: reg11 { 777 regulator-name = "reg11"; 778 regulator-min-microvolt = <1100000>; 779 regulator-max-microvolt = <1100000>; 780 }; 781 782 reg18: reg18 { 783 regulator-name = "reg18"; 784 regulator-min-microvolt = <1800000>; 785 regulator-max-microvolt = <1800000>; 786 }; 787 788 usb33: usb33 { 789 regulator-name = "usb33"; 790 regulator-min-microvolt = <3300000>; 791 regulator-max-microvolt = <3300000>; 792 }; 793 }; 794 795 exti: interrupt-controller@5000d000 { 796 compatible = "st,stm32mp1-exti", "syscon"; 797 interrupt-controller; 798 #interrupt-cells = <2>; 799 reg = <0x5000d000 0x400>; 800 interrupts-extended = 801 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 802 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 803 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 804 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 805 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 806 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 807 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 808 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 809 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 810 <&intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 811 <&intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 812 <&intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 813 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 814 <&intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 815 <&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 816 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 817 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 818 <0>, 819 <0>, 820 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 821 <0>, /* EXTI_20 */ 822 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 823 <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 824 <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 825 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 826 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 827 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 828 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 829 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 830 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 831 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 832 <&intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 833 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 834 <&intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 835 <0>, 836 <0>, 837 <0>, 838 <0>, 839 <0>, 840 <0>, 841 <0>, /* EXTI_40 */ 842 <0>, 843 <0>, 844 <0>, 845 <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 846 <0>, 847 <0>, 848 <&intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 849 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 850 <0>, 851 <&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 852 <0>, 853 <&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 854 <&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 855 <0>, 856 <0>, 857 <0>, 858 <0>, 859 <0>, 860 <0>, 861 <0>, /* EXTI_60 */ 862 <0>, 863 <0>, 864 <0>, 865 <0>, 866 <0>, 867 <0>, 868 <0>, 869 <&intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 870 <0>, 871 <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 872 }; 873 874 syscfg: syscon@50020000 { 875 compatible = "st,stm32mp157-syscfg", "syscon"; 876 reg = <0x50020000 0x400>; 877 clocks = <&rcc SYSCFG>; 878 }; 879 880 lptimer4: timer@50023000 { 881 compatible = "st,stm32-lptimer"; 882 reg = <0x50023000 0x400>; 883 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&rcc LPTIM4_K>; 885 clock-names = "mux"; 886 wakeup-source; 887 status = "disabled"; 888 889 pwm { 890 compatible = "st,stm32-pwm-lp"; 891 #pwm-cells = <3>; 892 status = "disabled"; 893 }; 894 895 timer { 896 compatible = "st,stm32-lptimer-timer"; 897 status = "disabled"; 898 }; 899 }; 900 901 lptimer5: timer@50024000 { 902 compatible = "st,stm32-lptimer"; 903 reg = <0x50024000 0x400>; 904 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&rcc LPTIM5_K>; 906 clock-names = "mux"; 907 wakeup-source; 908 status = "disabled"; 909 910 pwm { 911 compatible = "st,stm32-pwm-lp"; 912 #pwm-cells = <3>; 913 status = "disabled"; 914 }; 915 916 timer { 917 compatible = "st,stm32-lptimer-timer"; 918 status = "disabled"; 919 }; 920 }; 921 922 mdma: dma-controller@58000000 { 923 compatible = "st,stm32h7-mdma"; 924 reg = <0x58000000 0x1000>; 925 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&rcc MDMA>; 927 #dma-cells = <5>; 928 dma-channels = <32>; 929 dma-requests = <48>; 930 }; 931 932 crc1: crc@58009000 { 933 compatible = "st,stm32f7-crc"; 934 reg = <0x58009000 0x400>; 935 clocks = <&rcc CRC1>; 936 status = "disabled"; 937 }; 938 939 usbh_ohci: usb@5800c000 { 940 compatible = "generic-ohci"; 941 reg = <0x5800c000 0x1000>; 942 clocks = <&usbphyc>, <&rcc USBH>; 943 resets = <&rcc USBH_R>; 944 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 945 status = "disabled"; 946 }; 947 948 usbh_ehci: usb@5800d000 { 949 compatible = "generic-ehci"; 950 reg = <0x5800d000 0x1000>; 951 clocks = <&usbphyc>, <&rcc USBH>; 952 resets = <&rcc USBH_R>; 953 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 954 companion = <&usbh_ohci>; 955 status = "disabled"; 956 }; 957 958 iwdg2: watchdog@5a002000 { 959 compatible = "st,stm32mp1-iwdg"; 960 reg = <0x5a002000 0x400>; 961 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; 962 clock-names = "pclk", "lsi"; 963 status = "disabled"; 964 }; 965 966 rtc: rtc@5c004000 { 967 compatible = "st,stm32mp1-rtc"; 968 reg = <0x5c004000 0x400>; 969 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&scmi_clk CK_SCMI_RTCAPB>, 971 <&scmi_clk CK_SCMI_RTC>; 972 clock-names = "pclk", "rtc_ck"; 973 status = "disabled"; 974 }; 975 976 bsec: efuse@5c005000 { 977 compatible = "st,stm32mp13-bsec"; 978 reg = <0x5c005000 0x400>; 979 #address-cells = <1>; 980 #size-cells = <1>; 981 982 part_number_otp: part_number_otp@4 { 983 reg = <0x4 0x2>; 984 bits = <0 12>; 985 }; 986 ts_cal1: calib@5c { 987 reg = <0x5c 0x2>; 988 }; 989 ts_cal2: calib@5e { 990 reg = <0x5e 0x2>; 991 }; 992 ethernet_mac1_address: mac1@e4 { 993 reg = <0xe4 0x6>; 994 }; 995 ethernet_mac2_address: mac2@ea { 996 reg = <0xea 0x6>; 997 }; 998 }; 999 1000 etzpc: bus@5c007000 { 1001 compatible = "st,stm32-etzpc", "simple-bus"; 1002 reg = <0x5c007000 0x400>; 1003 #address-cells = <1>; 1004 #size-cells = <1>; 1005 #access-controller-cells = <1>; 1006 ranges; 1007 1008 adc_2: adc@48004000 { 1009 compatible = "st,stm32mp13-adc-core"; 1010 reg = <0x48004000 0x400>; 1011 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 1013 clock-names = "bus", "adc"; 1014 interrupt-controller; 1015 #interrupt-cells = <1>; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 access-controllers = <&etzpc 33>; 1019 status = "disabled"; 1020 1021 adc2: adc@0 { 1022 compatible = "st,stm32mp13-adc"; 1023 #io-channel-cells = <1>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 reg = <0x0>; 1027 interrupt-parent = <&adc_2>; 1028 interrupts = <0>; 1029 dmas = <&dmamux1 10 0x400 0x80000001>; 1030 dma-names = "rx"; 1031 status = "disabled"; 1032 1033 channel@13 { 1034 reg = <13>; 1035 label = "vrefint"; 1036 }; 1037 channel@14 { 1038 reg = <14>; 1039 label = "vddcore"; 1040 }; 1041 channel@16 { 1042 reg = <16>; 1043 label = "vddcpu"; 1044 }; 1045 channel@17 { 1046 reg = <17>; 1047 label = "vddq_ddr"; 1048 }; 1049 }; 1050 }; 1051 1052 usbotg_hs: usb@49000000 { 1053 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1054 reg = <0x49000000 0x40000>; 1055 clocks = <&rcc USBO_K>; 1056 clock-names = "otg"; 1057 resets = <&rcc USBO_R>; 1058 reset-names = "dwc2"; 1059 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1060 g-rx-fifo-size = <512>; 1061 g-np-tx-fifo-size = <32>; 1062 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1063 dr_mode = "otg"; 1064 otg-rev = <0x200>; 1065 usb33d-supply = <&scmi_usb33>; 1066 access-controllers = <&etzpc 34>; 1067 status = "disabled"; 1068 }; 1069 1070 usart1: serial@4c000000 { 1071 compatible = "st,stm32h7-uart"; 1072 reg = <0x4c000000 0x400>; 1073 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&rcc USART1_K>; 1075 resets = <&rcc USART1_R>; 1076 wakeup-source; 1077 dmas = <&dmamux1 41 0x400 0x5>, 1078 <&dmamux1 42 0x400 0x1>; 1079 dma-names = "rx", "tx"; 1080 access-controllers = <&etzpc 16>; 1081 status = "disabled"; 1082 }; 1083 1084 usart2: serial@4c001000 { 1085 compatible = "st,stm32h7-uart"; 1086 reg = <0x4c001000 0x400>; 1087 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 1088 clocks = <&rcc USART2_K>; 1089 resets = <&rcc USART2_R>; 1090 wakeup-source; 1091 dmas = <&dmamux1 43 0x400 0x5>, 1092 <&dmamux1 44 0x400 0x1>; 1093 dma-names = "rx", "tx"; 1094 access-controllers = <&etzpc 17>; 1095 status = "disabled"; 1096 }; 1097 1098 i2s4: audio-controller@4c002000 { 1099 compatible = "st,stm32h7-i2s"; 1100 reg = <0x4c002000 0x400>; 1101 #sound-dai-cells = <0>; 1102 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1103 dmas = <&dmamux1 83 0x400 0x01>, 1104 <&dmamux1 84 0x400 0x01>; 1105 dma-names = "rx", "tx"; 1106 access-controllers = <&etzpc 13>; 1107 status = "disabled"; 1108 }; 1109 1110 spi4: spi@4c002000 { 1111 compatible = "st,stm32h7-spi"; 1112 reg = <0x4c002000 0x400>; 1113 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&rcc SPI4_K>; 1115 resets = <&rcc SPI4_R>; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 dmas = <&dmamux1 83 0x400 0x01>, 1119 <&dmamux1 84 0x400 0x01>; 1120 dma-names = "rx", "tx"; 1121 access-controllers = <&etzpc 18>; 1122 status = "disabled"; 1123 }; 1124 1125 spi5: spi@4c003000 { 1126 compatible = "st,stm32h7-spi"; 1127 reg = <0x4c003000 0x400>; 1128 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&rcc SPI5_K>; 1130 resets = <&rcc SPI5_R>; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 dmas = <&dmamux1 85 0x400 0x01>, 1134 <&dmamux1 86 0x400 0x01>; 1135 dma-names = "rx", "tx"; 1136 access-controllers = <&etzpc 19>; 1137 status = "disabled"; 1138 }; 1139 1140 i2c3: i2c@4c004000 { 1141 compatible = "st,stm32mp13-i2c"; 1142 reg = <0x4c004000 0x400>; 1143 interrupt-names = "event", "error"; 1144 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&rcc I2C3_K>; 1147 resets = <&rcc I2C3_R>; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 dmas = <&dmamux1 73 0x400 0x1>, 1151 <&dmamux1 74 0x400 0x1>; 1152 dma-names = "rx", "tx"; 1153 st,syscfg-fmp = <&syscfg 0x4 0x4>; 1154 i2c-analog-filter; 1155 access-controllers = <&etzpc 20>; 1156 status = "disabled"; 1157 }; 1158 1159 i2c4: i2c@4c005000 { 1160 compatible = "st,stm32mp13-i2c"; 1161 reg = <0x4c005000 0x400>; 1162 interrupt-names = "event", "error"; 1163 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1165 clocks = <&rcc I2C4_K>; 1166 resets = <&rcc I2C4_R>; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 dmas = <&dmamux1 75 0x400 0x1>, 1170 <&dmamux1 76 0x400 0x1>; 1171 dma-names = "rx", "tx"; 1172 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1173 i2c-analog-filter; 1174 access-controllers = <&etzpc 21>; 1175 status = "disabled"; 1176 }; 1177 1178 i2c5: i2c@4c006000 { 1179 compatible = "st,stm32mp13-i2c"; 1180 reg = <0x4c006000 0x400>; 1181 interrupt-names = "event", "error"; 1182 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1184 clocks = <&rcc I2C5_K>; 1185 resets = <&rcc I2C5_R>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 dmas = <&dmamux1 115 0x400 0x1>, 1189 <&dmamux1 116 0x400 0x1>; 1190 dma-names = "rx", "tx"; 1191 st,syscfg-fmp = <&syscfg 0x4 0x10>; 1192 i2c-analog-filter; 1193 access-controllers = <&etzpc 22>; 1194 status = "disabled"; 1195 }; 1196 1197 timers12: timer@4c007000 { 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 compatible = "st,stm32-timers"; 1201 reg = <0x4c007000 0x400>; 1202 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1203 interrupt-names = "global"; 1204 clocks = <&rcc TIM12_K>; 1205 clock-names = "int"; 1206 access-controllers = <&etzpc 23>; 1207 status = "disabled"; 1208 1209 counter { 1210 compatible = "st,stm32-timer-counter"; 1211 status = "disabled"; 1212 }; 1213 1214 pwm { 1215 compatible = "st,stm32-pwm"; 1216 #pwm-cells = <3>; 1217 status = "disabled"; 1218 }; 1219 1220 timer@11 { 1221 compatible = "st,stm32h7-timer-trigger"; 1222 reg = <11>; 1223 status = "disabled"; 1224 }; 1225 }; 1226 1227 timers13: timer@4c008000 { 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 compatible = "st,stm32-timers"; 1231 reg = <0x4c008000 0x400>; 1232 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1233 interrupt-names = "global"; 1234 clocks = <&rcc TIM13_K>; 1235 clock-names = "int"; 1236 access-controllers = <&etzpc 24>; 1237 status = "disabled"; 1238 1239 counter { 1240 compatible = "st,stm32-timer-counter"; 1241 status = "disabled"; 1242 }; 1243 1244 pwm { 1245 compatible = "st,stm32-pwm"; 1246 #pwm-cells = <3>; 1247 status = "disabled"; 1248 }; 1249 1250 timer@12 { 1251 compatible = "st,stm32h7-timer-trigger"; 1252 reg = <12>; 1253 status = "disabled"; 1254 }; 1255 }; 1256 1257 timers14: timer@4c009000 { 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 compatible = "st,stm32-timers"; 1261 reg = <0x4c009000 0x400>; 1262 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1263 interrupt-names = "global"; 1264 clocks = <&rcc TIM14_K>; 1265 clock-names = "int"; 1266 access-controllers = <&etzpc 25>; 1267 status = "disabled"; 1268 1269 counter { 1270 compatible = "st,stm32-timer-counter"; 1271 status = "disabled"; 1272 }; 1273 1274 pwm { 1275 compatible = "st,stm32-pwm"; 1276 #pwm-cells = <3>; 1277 status = "disabled"; 1278 }; 1279 1280 timer@13 { 1281 compatible = "st,stm32h7-timer-trigger"; 1282 reg = <13>; 1283 status = "disabled"; 1284 }; 1285 }; 1286 1287 timers15: timer@4c00a000 { 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 compatible = "st,stm32-timers"; 1291 reg = <0x4c00a000 0x400>; 1292 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1293 interrupt-names = "global"; 1294 clocks = <&rcc TIM15_K>; 1295 clock-names = "int"; 1296 dmas = <&dmamux1 105 0x400 0x1>, 1297 <&dmamux1 106 0x400 0x1>, 1298 <&dmamux1 107 0x400 0x1>, 1299 <&dmamux1 108 0x400 0x1>; 1300 dma-names = "ch1", "up", "trig", "com"; 1301 access-controllers = <&etzpc 26>; 1302 status = "disabled"; 1303 1304 counter { 1305 compatible = "st,stm32-timer-counter"; 1306 status = "disabled"; 1307 }; 1308 1309 pwm { 1310 compatible = "st,stm32-pwm"; 1311 #pwm-cells = <3>; 1312 status = "disabled"; 1313 }; 1314 1315 timer@14 { 1316 compatible = "st,stm32h7-timer-trigger"; 1317 reg = <14>; 1318 status = "disabled"; 1319 }; 1320 }; 1321 1322 timers16: timer@4c00b000 { 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 compatible = "st,stm32-timers"; 1326 reg = <0x4c00b000 0x400>; 1327 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1328 interrupt-names = "global"; 1329 clocks = <&rcc TIM16_K>; 1330 clock-names = "int"; 1331 dmas = <&dmamux1 109 0x400 0x1>, 1332 <&dmamux1 110 0x400 0x1>; 1333 dma-names = "ch1", "up"; 1334 access-controllers = <&etzpc 27>; 1335 status = "disabled"; 1336 1337 counter { 1338 compatible = "st,stm32-timer-counter"; 1339 status = "disabled"; 1340 }; 1341 1342 pwm { 1343 compatible = "st,stm32-pwm"; 1344 #pwm-cells = <3>; 1345 status = "disabled"; 1346 }; 1347 1348 timer@15 { 1349 compatible = "st,stm32h7-timer-trigger"; 1350 reg = <15>; 1351 status = "disabled"; 1352 }; 1353 }; 1354 1355 timers17: timer@4c00c000 { 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 compatible = "st,stm32-timers"; 1359 reg = <0x4c00c000 0x400>; 1360 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1361 interrupt-names = "global"; 1362 clocks = <&rcc TIM17_K>; 1363 clock-names = "int"; 1364 dmas = <&dmamux1 111 0x400 0x1>, 1365 <&dmamux1 112 0x400 0x1>; 1366 dma-names = "ch1", "up"; 1367 access-controllers = <&etzpc 28>; 1368 status = "disabled"; 1369 1370 counter { 1371 compatible = "st,stm32-timer-counter"; 1372 status = "disabled"; 1373 }; 1374 1375 pwm { 1376 compatible = "st,stm32-pwm"; 1377 #pwm-cells = <3>; 1378 status = "disabled"; 1379 }; 1380 1381 timer@16 { 1382 compatible = "st,stm32h7-timer-trigger"; 1383 reg = <16>; 1384 status = "disabled"; 1385 }; 1386 }; 1387 1388 lptimer2: timer@50021000 { 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 compatible = "st,stm32-lptimer"; 1392 reg = <0x50021000 0x400>; 1393 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1394 clocks = <&rcc LPTIM2_K>; 1395 clock-names = "mux"; 1396 wakeup-source; 1397 access-controllers = <&etzpc 1>; 1398 status = "disabled"; 1399 1400 pwm { 1401 compatible = "st,stm32-pwm-lp"; 1402 #pwm-cells = <3>; 1403 status = "disabled"; 1404 }; 1405 1406 trigger@1 { 1407 compatible = "st,stm32-lptimer-trigger"; 1408 reg = <1>; 1409 status = "disabled"; 1410 }; 1411 1412 counter { 1413 compatible = "st,stm32-lptimer-counter"; 1414 status = "disabled"; 1415 }; 1416 1417 timer { 1418 compatible = "st,stm32-lptimer-timer"; 1419 status = "disabled"; 1420 }; 1421 }; 1422 1423 lptimer3: timer@50022000 { 1424 #address-cells = <1>; 1425 #size-cells = <0>; 1426 compatible = "st,stm32-lptimer"; 1427 reg = <0x50022000 0x400>; 1428 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1429 clocks = <&rcc LPTIM3_K>; 1430 clock-names = "mux"; 1431 wakeup-source; 1432 access-controllers = <&etzpc 2>; 1433 status = "disabled"; 1434 1435 pwm { 1436 compatible = "st,stm32-pwm-lp"; 1437 #pwm-cells = <3>; 1438 status = "disabled"; 1439 }; 1440 1441 trigger@2 { 1442 compatible = "st,stm32-lptimer-trigger"; 1443 reg = <2>; 1444 status = "disabled"; 1445 }; 1446 1447 timer { 1448 compatible = "st,stm32-lptimer-timer"; 1449 status = "disabled"; 1450 }; 1451 }; 1452 1453 hash: hash@54003000 { 1454 compatible = "st,stm32mp13-hash"; 1455 reg = <0x54003000 0x400>; 1456 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1457 clocks = <&rcc HASH1>; 1458 resets = <&rcc HASH1_R>; 1459 dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; 1460 dma-names = "in"; 1461 access-controllers = <&etzpc 41>; 1462 status = "disabled"; 1463 }; 1464 1465 rng: rng@54004000 { 1466 compatible = "st,stm32mp13-rng"; 1467 reg = <0x54004000 0x400>; 1468 clocks = <&rcc RNG1_K>; 1469 resets = <&rcc RNG1_R>; 1470 access-controllers = <&etzpc 40>; 1471 status = "disabled"; 1472 }; 1473 1474 fmc: memory-controller@58002000 { 1475 compatible = "st,stm32mp1-fmc2-ebi"; 1476 reg = <0x58002000 0x1000>; 1477 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1478 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1479 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1480 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1481 <4 0 0x80000000 0x10000000>; /* NAND */ 1482 #address-cells = <2>; 1483 #size-cells = <1>; 1484 clocks = <&rcc FMC_K>; 1485 resets = <&rcc FMC_R>; 1486 access-controllers = <&etzpc 54>; 1487 status = "disabled"; 1488 1489 nand-controller@4,0 { 1490 compatible = "st,stm32mp1-fmc2-nfc"; 1491 reg = <4 0x00000000 0x1000>, 1492 <4 0x08010000 0x1000>, 1493 <4 0x08020000 0x1000>, 1494 <4 0x01000000 0x1000>, 1495 <4 0x09010000 0x1000>, 1496 <4 0x09020000 0x1000>; 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1500 dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, 1501 <&mdma 24 0x2 0x12000a08 0x0 0x0>, 1502 <&mdma 25 0x2 0x12000a0a 0x0 0x0>; 1503 dma-names = "tx", "rx", "ecc"; 1504 status = "disabled"; 1505 }; 1506 }; 1507 1508 qspi: spi@58003000 { 1509 compatible = "st,stm32f469-qspi"; 1510 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1511 reg-names = "qspi", "qspi_mm"; 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1515 dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, 1516 <&mdma 26 0x2 0x10100008 0x0 0x0>; 1517 dma-names = "tx", "rx"; 1518 clocks = <&rcc QSPI_K>; 1519 resets = <&rcc QSPI_R>; 1520 access-controllers = <&etzpc 55>; 1521 status = "disabled"; 1522 }; 1523 1524 sdmmc1: mmc@58005000 { 1525 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1526 arm,primecell-periphid = <0x20253180>; 1527 reg = <0x58005000 0x1000>, <0x58006000 0x1000>; 1528 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1529 clocks = <&rcc SDMMC1_K>; 1530 clock-names = "apb_pclk"; 1531 resets = <&rcc SDMMC1_R>; 1532 cap-sd-highspeed; 1533 cap-mmc-highspeed; 1534 max-frequency = <130000000>; 1535 access-controllers = <&etzpc 50>; 1536 status = "disabled"; 1537 }; 1538 1539 sdmmc2: mmc@58007000 { 1540 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1541 arm,primecell-periphid = <0x20253180>; 1542 reg = <0x58007000 0x1000>, <0x58008000 0x1000>; 1543 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1544 clocks = <&rcc SDMMC2_K>; 1545 clock-names = "apb_pclk"; 1546 resets = <&rcc SDMMC2_R>; 1547 cap-sd-highspeed; 1548 cap-mmc-highspeed; 1549 max-frequency = <130000000>; 1550 access-controllers = <&etzpc 51>; 1551 status = "disabled"; 1552 }; 1553 1554 ethernet1: ethernet@5800a000 { 1555 compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; 1556 reg = <0x5800a000 0x2000>; 1557 reg-names = "stmmaceth"; 1558 interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1559 <&exti 68 1>; 1560 interrupt-names = "macirq", "eth_wake_irq"; 1561 clock-names = "stmmaceth", 1562 "mac-clk-tx", 1563 "mac-clk-rx", 1564 "ethstp", 1565 "eth-ck"; 1566 clocks = <&rcc ETH1MAC>, 1567 <&rcc ETH1TX>, 1568 <&rcc ETH1RX>, 1569 <&rcc ETH1STP>, 1570 <&rcc ETH1CK_K>; 1571 st,syscon = <&syscfg 0x4 0xff0000>; 1572 snps,mixed-burst; 1573 snps,pbl = <2>; 1574 snps,axi-config = <&stmmac_axi_config_1>; 1575 snps,tso; 1576 access-controllers = <&etzpc 48>; 1577 status = "disabled"; 1578 1579 stmmac_axi_config_1: stmmac-axi-config { 1580 snps,blen = <0 0 0 0 16 8 4>; 1581 snps,rd_osr_lmt = <0x7>; 1582 snps,wr_osr_lmt = <0x7>; 1583 }; 1584 }; 1585 1586 usbphyc: usbphyc@5a006000 { 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 #clock-cells = <0>; 1590 compatible = "st,stm32mp1-usbphyc"; 1591 reg = <0x5a006000 0x1000>; 1592 clocks = <&rcc USBPHY_K>; 1593 resets = <&rcc USBPHY_R>; 1594 vdda1v1-supply = <&scmi_reg11>; 1595 vdda1v8-supply = <&scmi_reg18>; 1596 access-controllers = <&etzpc 5>; 1597 status = "disabled"; 1598 1599 usbphyc_port0: usb-phy@0 { 1600 #phy-cells = <0>; 1601 reg = <0>; 1602 }; 1603 1604 usbphyc_port1: usb-phy@1 { 1605 #phy-cells = <1>; 1606 reg = <1>; 1607 }; 1608 }; 1609 }; 1610 1611 /* 1612 * Break node order to solve dependency probe issue between 1613 * pinctrl and exti. 1614 */ 1615 pinctrl: pinctrl@50002000 { 1616 #address-cells = <1>; 1617 #size-cells = <1>; 1618 compatible = "st,stm32mp135-pinctrl"; 1619 ranges = <0 0x50002000 0x8400>; 1620 interrupt-parent = <&exti>; 1621 st,syscfg = <&exti 0x60 0xff>; 1622 1623 gpioa: gpio@50002000 { 1624 gpio-controller; 1625 #gpio-cells = <2>; 1626 interrupt-controller; 1627 #interrupt-cells = <2>; 1628 reg = <0x0 0x400>; 1629 clocks = <&rcc GPIOA>; 1630 st,bank-name = "GPIOA"; 1631 ngpios = <16>; 1632 gpio-ranges = <&pinctrl 0 0 16>; 1633 }; 1634 1635 gpiob: gpio@50003000 { 1636 gpio-controller; 1637 #gpio-cells = <2>; 1638 interrupt-controller; 1639 #interrupt-cells = <2>; 1640 reg = <0x1000 0x400>; 1641 clocks = <&rcc GPIOB>; 1642 st,bank-name = "GPIOB"; 1643 ngpios = <16>; 1644 gpio-ranges = <&pinctrl 0 16 16>; 1645 }; 1646 1647 gpioc: gpio@50004000 { 1648 gpio-controller; 1649 #gpio-cells = <2>; 1650 interrupt-controller; 1651 #interrupt-cells = <2>; 1652 reg = <0x2000 0x400>; 1653 clocks = <&rcc GPIOC>; 1654 st,bank-name = "GPIOC"; 1655 ngpios = <16>; 1656 gpio-ranges = <&pinctrl 0 32 16>; 1657 }; 1658 1659 gpiod: gpio@50005000 { 1660 gpio-controller; 1661 #gpio-cells = <2>; 1662 interrupt-controller; 1663 #interrupt-cells = <2>; 1664 reg = <0x3000 0x400>; 1665 clocks = <&rcc GPIOD>; 1666 st,bank-name = "GPIOD"; 1667 ngpios = <16>; 1668 gpio-ranges = <&pinctrl 0 48 16>; 1669 }; 1670 1671 gpioe: gpio@50006000 { 1672 gpio-controller; 1673 #gpio-cells = <2>; 1674 interrupt-controller; 1675 #interrupt-cells = <2>; 1676 reg = <0x4000 0x400>; 1677 clocks = <&rcc GPIOE>; 1678 st,bank-name = "GPIOE"; 1679 ngpios = <16>; 1680 gpio-ranges = <&pinctrl 0 64 16>; 1681 }; 1682 1683 gpiof: gpio@50007000 { 1684 gpio-controller; 1685 #gpio-cells = <2>; 1686 interrupt-controller; 1687 #interrupt-cells = <2>; 1688 reg = <0x5000 0x400>; 1689 clocks = <&rcc GPIOF>; 1690 st,bank-name = "GPIOF"; 1691 ngpios = <16>; 1692 gpio-ranges = <&pinctrl 0 80 16>; 1693 }; 1694 1695 gpiog: gpio@50008000 { 1696 gpio-controller; 1697 #gpio-cells = <2>; 1698 interrupt-controller; 1699 #interrupt-cells = <2>; 1700 reg = <0x6000 0x400>; 1701 clocks = <&rcc GPIOG>; 1702 st,bank-name = "GPIOG"; 1703 ngpios = <16>; 1704 gpio-ranges = <&pinctrl 0 96 16>; 1705 }; 1706 1707 gpioh: gpio@50009000 { 1708 gpio-controller; 1709 #gpio-cells = <2>; 1710 interrupt-controller; 1711 #interrupt-cells = <2>; 1712 reg = <0x7000 0x400>; 1713 clocks = <&rcc GPIOH>; 1714 st,bank-name = "GPIOH"; 1715 ngpios = <15>; 1716 gpio-ranges = <&pinctrl 0 112 15>; 1717 }; 1718 1719 gpioi: gpio@5000a000 { 1720 gpio-controller; 1721 #gpio-cells = <2>; 1722 interrupt-controller; 1723 #interrupt-cells = <2>; 1724 reg = <0x8000 0x400>; 1725 clocks = <&rcc GPIOI>; 1726 st,bank-name = "GPIOI"; 1727 ngpios = <8>; 1728 gpio-ranges = <&pinctrl 0 128 8>; 1729 }; 1730 }; 1731 }; 1732}; 1733