1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6*724ba675SRob Herring * http://www.samsung.com 7*724ba675SRob Herring * 8*724ba675SRob Herring * Device tree source file for Samsung's ARTIK5 evaluation board 9*724ba675SRob Herring * which is based on Samsung Exynos3250 SoC. 10*724ba675SRob Herring */ 11*724ba675SRob Herring 12*724ba675SRob Herring/dts-v1/; 13*724ba675SRob Herring#include "exynos3250-artik5.dtsi" 14*724ba675SRob Herring 15*724ba675SRob Herring/ { 16*724ba675SRob Herring model = "Samsung ARTIK5 evaluation board"; 17*724ba675SRob Herring compatible = "samsung,artik5-eval", "samsung,artik5", 18*724ba675SRob Herring "samsung,exynos3250", "samsung,exynos3"; 19*724ba675SRob Herring 20*724ba675SRob Herring aliases { 21*724ba675SRob Herring mmc0 = &mshc_2; 22*724ba675SRob Herring }; 23*724ba675SRob Herring}; 24*724ba675SRob Herring 25*724ba675SRob Herring&mshc_2 { 26*724ba675SRob Herring cap-sd-highspeed; 27*724ba675SRob Herring disable-wp; 28*724ba675SRob Herring vqmmc-supply = <&ldo3_reg>; 29*724ba675SRob Herring card-detect-delay = <200>; 30*724ba675SRob Herring clock-frequency = <100000000>; 31*724ba675SRob Herring max-frequency = <100000000>; 32*724ba675SRob Herring samsung,dw-mshc-ciu-div = <1>; 33*724ba675SRob Herring samsung,dw-mshc-sdr-timing = <0 1>; 34*724ba675SRob Herring samsung,dw-mshc-ddr-timing = <1 2>; 35*724ba675SRob Herring pinctrl-names = "default"; 36*724ba675SRob Herring pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>; 37*724ba675SRob Herring bus-width = <4>; 38*724ba675SRob Herring status = "okay"; 39*724ba675SRob Herring}; 40*724ba675SRob Herring 41*724ba675SRob Herring&serial_2 { 42*724ba675SRob Herring status = "okay"; 43*724ba675SRob Herring}; 44*724ba675SRob Herring 45*724ba675SRob Herring&spi_0 { 46*724ba675SRob Herring status = "okay"; 47*724ba675SRob Herring cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>; 48*724ba675SRob Herring 49*724ba675SRob Herring assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, 50*724ba675SRob Herring <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>; 51*724ba675SRob Herring assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ 52*724ba675SRob Herring <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */ 53*724ba675SRob Herring <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */ 54*724ba675SRob Herring <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */ 55*724ba675SRob Herring 56*724ba675SRob Herring ethernet@0 { 57*724ba675SRob Herring compatible = "asix,ax88796c"; 58*724ba675SRob Herring reg = <0x0>; 59*724ba675SRob Herring local-mac-address = [00 00 00 00 00 00]; /* Filled in by a boot-loader */ 60*724ba675SRob Herring interrupt-parent = <&gpx2>; 61*724ba675SRob Herring interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 62*724ba675SRob Herring spi-max-frequency = <40000000>; 63*724ba675SRob Herring reset-gpios = <&gpe0 2 GPIO_ACTIVE_LOW>; 64*724ba675SRob Herring 65*724ba675SRob Herring controller-data { 66*724ba675SRob Herring samsung,spi-feedback-delay = <2>; 67*724ba675SRob Herring }; 68*724ba675SRob Herring }; 69*724ba675SRob Herring}; 70