1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. 5 */ 6 7/ { 8 compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126"; 9 10 aliases { 11 mmc0 = &emmc; 12 }; 13 14 vccio_flash: regulator-vccio-flash { 15 compatible = "regulator-fixed"; 16 enable-active-high; 17 gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; 18 pinctrl-names = "default"; 19 pinctrl-0 = <&flash_vol_sel>; 20 regulator-name = "vccio_flash"; 21 regulator-always-on; 22 regulator-boot-on; 23 regulator-min-microvolt = <1800000>; 24 regulator-max-microvolt = <1800000>; 25 vin-supply = <&vcc_3v3>; 26 }; 27 28 sdio_pwrseq: pwrseq-sdio { 29 compatible = "mmc-pwrseq-simple"; 30 clocks = <&rk809 1>; 31 clock-names = "ext_clock"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&wifi_enable_h>; 34 reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; 35 }; 36}; 37 38&cpu0 { 39 cpu-supply = <&vdd_arm>; 40}; 41 42&emmc { 43 bus-width = <8>; 44 non-removable; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>; 47 rockchip,default-sample-phase = <90>; 48 vmmc-supply = <&vcc_3v3>; 49 vqmmc-supply = <&vccio_flash>; 50 status = "okay"; 51}; 52 53&i2c0 { 54 clock-frequency = <400000>; 55 status = "okay"; 56 57 rk809: pmic@20 { 58 compatible = "rockchip,rk809"; 59 reg = <0x20>; 60 interrupt-parent = <&gpio0>; 61 interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>; 62 #clock-cells = <1>; 63 clock-output-names = "rk808-clkout1", "rk808-clkout2"; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pmic_int_l>; 66 rockchip,system-power-controller; 67 wakeup-source; 68 69 vcc1-supply = <&vcc5v0_sys>; 70 vcc2-supply = <&vcc5v0_sys>; 71 vcc3-supply = <&vcc5v0_sys>; 72 vcc4-supply = <&vcc5v0_sys>; 73 vcc5-supply = <&vcc_buck5>; 74 vcc6-supply = <&vcc_buck5>; 75 vcc7-supply = <&vcc5v0_sys>; 76 vcc8-supply = <&vcc3v3_sys>; 77 vcc9-supply = <&vcc5v0_sys>; 78 79 regulators { 80 vdd_npu_vepu: DCDC_REG1 { 81 regulator-name = "vdd_npu_vepu"; 82 regulator-always-on; 83 regulator-boot-on; 84 regulator-initial-mode = <0x2>; 85 regulator-min-microvolt = <650000>; 86 regulator-max-microvolt = <950000>; 87 regulator-ramp-delay = <6001>; 88 regulator-state-mem { 89 regulator-off-in-suspend; 90 }; 91 }; 92 93 vdd_arm: DCDC_REG2 { 94 regulator-name = "vdd_arm"; 95 regulator-always-on; 96 regulator-boot-on; 97 regulator-initial-mode = <0x2>; 98 regulator-min-microvolt = <725000>; 99 regulator-max-microvolt = <1350000>; 100 regulator-ramp-delay = <6001>; 101 regulator-state-mem { 102 regulator-off-in-suspend; 103 }; 104 }; 105 106 vcc_ddr: DCDC_REG3 { 107 regulator-name = "vcc_ddr"; 108 regulator-always-on; 109 regulator-boot-on; 110 regulator-initial-mode = <0x2>; 111 regulator-state-mem { 112 regulator-on-in-suspend; 113 }; 114 }; 115 116 vcc3v3_sys: DCDC_REG4 { 117 regulator-name = "vcc3v3_sys"; 118 regulator-always-on; 119 regulator-boot-on; 120 regulator-initial-mode = <0x2>; 121 regulator-min-microvolt = <3300000>; 122 regulator-max-microvolt = <3300000>; 123 regulator-state-mem { 124 regulator-on-in-suspend; 125 regulator-suspend-microvolt = <3300000>; 126 }; 127 }; 128 129 vcc_buck5: DCDC_REG5 { 130 regulator-name = "vcc_buck5"; 131 regulator-always-on; 132 regulator-boot-on; 133 regulator-min-microvolt = <2200000>; 134 regulator-max-microvolt = <2200000>; 135 regulator-state-mem { 136 regulator-on-in-suspend; 137 regulator-suspend-microvolt = <2200000>; 138 }; 139 }; 140 141 vcc_0v8: LDO_REG1 { 142 regulator-name = "vcc_0v8"; 143 regulator-always-on; 144 regulator-boot-on; 145 regulator-min-microvolt = <800000>; 146 regulator-max-microvolt = <800000>; 147 regulator-state-mem { 148 regulator-off-in-suspend; 149 }; 150 }; 151 152 vcc1v8_pmu: LDO_REG2 { 153 regulator-name = "vcc1v8_pmu"; 154 regulator-always-on; 155 regulator-boot-on; 156 regulator-min-microvolt = <1800000>; 157 regulator-max-microvolt = <1800000>; 158 regulator-state-mem { 159 regulator-on-in-suspend; 160 regulator-suspend-microvolt = <1800000>; 161 }; 162 }; 163 164 vdd0v8_pmu: LDO_REG3 { 165 regulator-name = "vcc0v8_pmu"; 166 regulator-always-on; 167 regulator-boot-on; 168 regulator-min-microvolt = <800000>; 169 regulator-max-microvolt = <800000>; 170 regulator-state-mem { 171 regulator-on-in-suspend; 172 regulator-suspend-microvolt = <800000>; 173 }; 174 }; 175 176 vcc_1v8: LDO_REG4 { 177 regulator-name = "vcc_1v8"; 178 regulator-always-on; 179 regulator-boot-on; 180 regulator-min-microvolt = <1800000>; 181 regulator-max-microvolt = <1800000>; 182 regulator-state-mem { 183 regulator-on-in-suspend; 184 regulator-suspend-microvolt = <1800000>; 185 }; 186 }; 187 188 vcc_dovdd: LDO_REG5 { 189 regulator-name = "vcc_dovdd"; 190 regulator-boot-on; 191 regulator-min-microvolt = <1800000>; 192 regulator-max-microvolt = <1800000>; 193 regulator-state-mem { 194 regulator-off-in-suspend; 195 }; 196 }; 197 198 vcc_dvdd: LDO_REG6 { 199 regulator-name = "vcc_dvdd"; 200 regulator-min-microvolt = <1200000>; 201 regulator-max-microvolt = <1200000>; 202 regulator-state-mem { 203 regulator-off-in-suspend; 204 }; 205 }; 206 207 vcc_avdd: LDO_REG7 { 208 regulator-name = "vcc_avdd"; 209 regulator-min-microvolt = <2800000>; 210 regulator-max-microvolt = <2800000>; 211 regulator-state-mem { 212 regulator-off-in-suspend; 213 }; 214 }; 215 216 vccio_sd: LDO_REG8 { 217 regulator-name = "vccio_sd"; 218 regulator-always-on; 219 regulator-boot-on; 220 regulator-min-microvolt = <1800000>; 221 regulator-max-microvolt = <3300000>; 222 regulator-state-mem { 223 regulator-off-in-suspend; 224 }; 225 }; 226 227 vcc3v3_sd: LDO_REG9 { 228 regulator-name = "vcc3v3_sd"; 229 regulator-always-on; 230 regulator-boot-on; 231 regulator-min-microvolt = <3300000>; 232 regulator-max-microvolt = <3300000>; 233 regulator-state-mem { 234 regulator-off-in-suspend; 235 }; 236 }; 237 238 vcc_5v0: SWITCH_REG1 { 239 regulator-name = "vcc_5v0"; 240 }; 241 242 vcc_3v3: SWITCH_REG2 { 243 regulator-name = "vcc_3v3"; 244 regulator-always-on; 245 regulator-boot-on; 246 }; 247 }; 248 }; 249}; 250 251&pinctrl { 252 bt { 253 bt_enable: bt-enable { 254 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 255 }; 256 }; 257 258 flash { 259 flash_vol_sel: flash-vol-sel { 260 rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 261 }; 262 }; 263 264 pmic { 265 pmic_int_l: pmic-int-l { 266 rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 267 }; 268 }; 269 270 wifi { 271 wifi_enable_h: wifi-enable-h { 272 rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 273 }; 274 }; 275}; 276 277&pmu_io_domains { 278 pmuio0-supply = <&vcc1v8_pmu>; 279 pmuio1-supply = <&vcc3v3_sys>; 280 vccio1-supply = <&vccio_flash>; 281 vccio2-supply = <&vccio_sd>; 282 vccio3-supply = <&vcc_1v8>; 283 vccio4-supply = <&vcc_dovdd>; 284 vccio5-supply = <&vcc_1v8>; 285 vccio6-supply = <&vcc_1v8>; 286 vccio7-supply = <&vcc_dovdd>; 287 status = "okay"; 288}; 289 290&saradc { 291 vref-supply = <&vcc_1v8>; 292 status = "okay"; 293}; 294 295&sfc { 296 pinctrl-names = "default"; 297 pinctrl-0 = <&fspi_pins>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 status = "okay"; 301 302 flash@0 { 303 compatible = "jedec,spi-nor"; 304 reg = <0>; 305 spi-max-frequency = <50000000>; 306 spi-rx-bus-width = <4>; 307 spi-tx-bus-width = <1>; 308 }; 309}; 310 311&sdio { 312 bus-width = <4>; 313 cap-sd-highspeed; 314 cap-sdio-irq; 315 keep-power-in-suspend; 316 max-frequency = <100000000>; 317 mmc-pwrseq = <&sdio_pwrseq>; 318 non-removable; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; 321 rockchip,default-sample-phase = <90>; 322 sd-uhs-sdr104; 323 vmmc-supply = <&vcc3v3_sys>; 324 vqmmc-supply = <&vcc_1v8>; 325 status = "okay"; 326 #address-cells = <1>; 327 #size-cells = <0>; 328}; 329 330&uart0 { 331 pinctrl-names = "default"; 332 pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; 333 status = "okay"; 334 335 bluetooth { 336 compatible = "qcom,qca9377-bt"; 337 clocks = <&rk809 1>; 338 enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */ 339 max-speed = <2000000>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&bt_enable>; 342 vddxo-supply = <&vcc3v3_sys>; 343 vddio-supply = <&vcc_1v8>; 344 }; 345}; 346