1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2026 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rv1103b-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/soc/rockchip,boot-mode.h> 12 13/ { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 compatible = "rockchip,rv1103b"; 18 19 interrupt-parent = <&gic>; 20 21 arm-pmu { 22 compatible = "arm,cortex-a7-pmu"; 23 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 24 interrupt-affinity = <&cpu0>; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "arm,cortex-a7"; 33 reg = <0x0>; 34 clocks = <&cru ARMCLK>; 35 device_type = "cpu"; 36 }; 37 }; 38 39 timer { 40 compatible = "arm,armv7-timer"; 41 clock-frequency = <24000000>; 42 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, 43 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 44 }; 45 46 xin24m: oscillator-24m { 47 compatible = "fixed-clock"; 48 clock-frequency = <24000000>; 49 clock-output-names = "xin24m"; 50 #clock-cells = <0>; 51 }; 52 53 pinctrl: pinctrl { 54 compatible = "rockchip,rv1103b-pinctrl"; 55 rockchip,grf = <&ioc>; 56 ranges; 57 #address-cells = <1>; 58 #size-cells = <1>; 59 60 gpio0: gpio@20520000 { 61 compatible = "rockchip,gpio-bank"; 62 reg = <0x20520000 0x200>; 63 clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>; 64 gpio-controller; 65 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 66 interrupt-controller; 67 #gpio-cells = <2>; 68 #interrupt-cells = <2>; 69 }; 70 71 gpio1: gpio@20d80000 { 72 compatible = "rockchip,gpio-bank"; 73 reg = <0x20d80000 0x200>; 74 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 75 gpio-controller; 76 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 77 interrupt-controller; 78 #gpio-cells = <2>; 79 #interrupt-cells = <2>; 80 }; 81 82 gpio2: gpio@20840000 { 83 compatible = "rockchip,gpio-bank"; 84 reg = <0x20840000 0x200>; 85 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 86 gpio-controller; 87 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 88 interrupt-controller; 89 #gpio-cells = <2>; 90 #interrupt-cells = <2>; 91 }; 92 }; 93 94 soc { 95 compatible = "simple-bus"; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges; 99 100 cru: clock-controller@20000000 { 101 compatible = "rockchip,rv1103b-cru"; 102 reg = <0x20000000 0x81000>; 103 #clock-cells = <1>; 104 #reset-cells = <1>; 105 }; 106 107 pmu_grf: syscon@20160000 { 108 compatible = "rockchip,rv1103b-pmu-grf", "syscon", "simple-mfd"; 109 reg = <0x20160000 0x1000>; 110 111 reboot_mode: reboot-mode { 112 compatible = "syscon-reboot-mode"; 113 offset = <0x200>; 114 mode-normal = <BOOT_NORMAL>; 115 mode-recovery = <BOOT_RECOVERY>; 116 mode-bootloader = <BOOT_FASTBOOT>; 117 mode-loader = <BOOT_BL_DOWNLOAD>; 118 }; 119 }; 120 121 ioc: syscon@20170000 { 122 compatible = "rockchip,rv1103b-ioc", "syscon"; 123 reg = <0x20170000 0x60000>; 124 }; 125 126 gic: interrupt-controller@20411000 { 127 compatible = "arm,gic-400"; 128 reg = <0x20411000 0x1000>, 129 <0x20412000 0x2000>, 130 <0x20414000 0x2000>, 131 <0x20416000 0x2000>; 132 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 133 interrupt-controller; 134 #interrupt-cells = <3>; 135 #address-cells = <0>; 136 }; 137 138 uart0: serial@20540000 { 139 compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart"; 140 reg = <0x20540000 0x100>; 141 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 142 clock-names = "baudclk", "apb_pclk"; 143 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&uart0m0_xfer>; 146 reg-shift = <2>; 147 reg-io-width = <4>; 148 status = "disabled"; 149 }; 150 151 sdmmc1: mmc@20650000 { 152 compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc"; 153 reg = <0x20650000 0x4000>; 154 clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>; 155 clock-names = "biu", "ciu"; 156 fifo-depth = <0x100>; 157 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 158 max-frequency = <150000000>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; 161 status = "disabled"; 162 }; 163 164 uart1: serial@20870000 { 165 compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart"; 166 reg = <0x20870000 0x100>; 167 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 168 clock-names = "baudclk", "apb_pclk"; 169 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&uart1m0_xfer>; 172 reg-shift = <2>; 173 reg-io-width = <4>; 174 status = "disabled"; 175 }; 176 177 uart2: serial@20880000 { 178 compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart"; 179 reg = <0x20880000 0x100>; 180 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 181 clock-names = "baudclk", "apb_pclk"; 182 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 183 pinctrl-names = "default"; 184 pinctrl-0 = <&uart2m0_xfer>; 185 reg-shift = <2>; 186 reg-io-width = <4>; 187 status = "disabled"; 188 }; 189 190 sdmmc0: mmc@20d20000 { 191 compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc"; 192 reg = <0x20d20000 0x4000>; 193 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>; 194 clock-names = "biu", "ciu"; 195 fifo-depth = <0x100>; 196 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 197 max-frequency = <150000000>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&sdmmc0_det &sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4>; 200 status = "disabled"; 201 }; 202 203 emmc: mmc@20d30000 { 204 compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc"; 205 reg = <0x20d30000 0x4000>; 206 clocks = <&cru HCLK_EMMC>, <&cru CCLK_EMMC>; 207 clock-names = "biu", "ciu"; 208 fifo-depth = <0x100>; 209 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 210 max-frequency = <150000000>; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>; 213 status = "disabled"; 214 }; 215 216 fspi0: spi@20d40000 { 217 compatible = "rockchip,sfc"; 218 reg = <0x20d40000 0x4000>; 219 clocks = <&cru SCLK_SFC_2X>, <&cru HCLK_SFC>; 220 clock-names = "clk_sfc", "hclk_sfc"; 221 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&fspi_bus4 &fspi_cs0 &fspi_clk>; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 status = "disabled"; 227 }; 228 229 system_sram: sram@210f6000 { 230 compatible = "mmio-sram"; 231 reg = <0x210f6000 0x8000>; 232 ranges = <0 0x210f6000 0x8000>; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 }; 236 }; 237}; 238 239#include "rv1103b-pinctrl.dtsi" 240