1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2025 plan44.ch/luz 5 * Copyright (c) 2026 Onion Corporation 6 */ 7 8/dts-v1/; 9 10#include "rv1103b.dtsi" 11 12/ { 13 sdio_pwrseq: sdio-pwrseq { 14 compatible = "mmc-pwrseq-simple"; 15 pinctrl-names = "default"; 16 pinctrl-0 = <&wifi_enable_h>; 17 post-power-on-delay-ms = <300>; 18 reset-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; 19 }; 20 21 vcc3v3_sd: vcc3v3-sd { 22 compatible = "regulator-fixed"; 23 gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 24 pinctrl-names = "default"; 25 pinctrl-0 = <&sdmmc_pwren>; 26 regulator-name = "vcc3v3_sd"; 27 regulator-min-microvolt = <3300000>; 28 regulator-max-microvolt = <3300000>; 29 }; 30 31 vccio_sd: vccio-sd { 32 compatible = "regulator-gpio"; 33 gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&sdmmc_volt>; 36 regulator-name = "vccio_sd"; 37 regulator-min-microvolt = <1800000>; 38 regulator-max-microvolt = <3300000>; 39 states = <3300000 1 1800000 0>; 40 }; 41}; 42 43&uart0 { 44 bootph-all; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&uart0m0_xfer>; 47}; 48 49&fspi0 { 50 spi_nand: flash@0 { 51 compatible = "spi-nand"; 52 reg = <0>; 53 bootph-pre-ram; 54 bootph-some-ram; 55 spi-max-frequency = <75000000>; 56 spi-rx-bus-width = <4>; 57 spi-tx-bus-width = <1>; 58 59 partitions { 60 compatible = "fixed-partitions"; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 64 partition@0 { 65 reg = <0x00000000 0x00040000>; 66 label = "env"; 67 }; 68 69 partition@40000 { 70 reg = <0x00040000 0x00100000>; 71 label = "idblock"; 72 read-only; 73 }; 74 75 partition@140000 { 76 reg = <0x00140000 0x00100000>; 77 label = "uboot"; 78 read-only; 79 }; 80 81 partition@240000 { 82 reg = <0x00240000 0x00800000>; 83 label = "boot"; 84 }; 85 86 partition@a40000 { 87 reg = <0x00a40000 0x0f5c0000>; 88 label = "ubi"; 89 }; 90 }; 91 }; 92}; 93 94&sdmmc0 { 95 bus-width = <4>; 96 cap-mmc-highspeed; 97 cap-sd-highspeed; 98 disable-wp; 99 no-sdio; 100 no-mmc; 101 sd-uhs-sdr104; 102 vmmc-supply = <&vcc3v3_sd>; 103 vqmmc-supply = <&vccio_sd>; 104 status = "disabled"; 105}; 106 107&sdmmc1 { 108 bus-width = <4>; 109 cap-sd-highspeed; 110 cap-sdio-irq; 111 keep-power-in-suspend; 112 mmc-pwrseq = <&sdio_pwrseq>; 113 no-sd; 114 no-mmc; 115 non-removable; 116 pinctrl-names = "default"; 117 pinctrl-0 = <&sdmmc1_cmd &sdmmc1_clk &sdmmc1_bus4>; 118 status = "disabled"; 119}; 120 121&pinctrl { 122 sdio-pwrseq { 123 /omit-if-no-ref/ 124 wifi_enable_h: wifi-enable-h { 125 rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 126 }; 127 }; 128 129 sdmmc { 130 /omit-if-no-ref/ 131 sdmmc_pwren: sdmmc-pwren { 132 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 133 }; 134 135 /omit-if-no-ref/ 136 sdmmc_volt: sdmmc-volt { 137 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 138 }; 139 }; 140 141 wireless-wlan { 142 /omit-if-no-ref/ 143 wifi_host_wake_irq: wifi-host-wake-irq { 144 rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 145 }; 146 }; 147}; 148