1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-msm8974.h> 10#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 11#include <dt-bindings/clock/qcom,rpmcc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/reset/qcom,gcc-msm8974.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 interrupt-parent = <&intc>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo_board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <19200000>; 29 }; 30 31 sleep_clk: sleep_clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <32768>; 35 }; 36 }; 37 38 cpus { 39 #address-cells = <1>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 compatible = "arm,cortex-a7"; 44 enable-method = "qcom,msm8226-smp"; 45 device_type = "cpu"; 46 reg = <0>; 47 next-level-cache = <&l2>; 48 clocks = <&apcs>; 49 operating-points-v2 = <&cpu_opp_table>; 50 qcom,acc = <&acc0>; 51 qcom,saw = <&saw0>; 52 #cooling-cells = <2>; 53 }; 54 55 cpu1: cpu@1 { 56 compatible = "arm,cortex-a7"; 57 enable-method = "qcom,msm8226-smp"; 58 device_type = "cpu"; 59 reg = <1>; 60 next-level-cache = <&l2>; 61 clocks = <&apcs>; 62 operating-points-v2 = <&cpu_opp_table>; 63 qcom,acc = <&acc1>; 64 qcom,saw = <&saw1>; 65 #cooling-cells = <2>; 66 }; 67 68 cpu2: cpu@2 { 69 compatible = "arm,cortex-a7"; 70 enable-method = "qcom,msm8226-smp"; 71 device_type = "cpu"; 72 reg = <2>; 73 next-level-cache = <&l2>; 74 clocks = <&apcs>; 75 operating-points-v2 = <&cpu_opp_table>; 76 qcom,acc = <&acc2>; 77 qcom,saw = <&saw2>; 78 #cooling-cells = <2>; 79 }; 80 81 cpu3: cpu@3 { 82 compatible = "arm,cortex-a7"; 83 enable-method = "qcom,msm8226-smp"; 84 device_type = "cpu"; 85 reg = <3>; 86 next-level-cache = <&l2>; 87 clocks = <&apcs>; 88 operating-points-v2 = <&cpu_opp_table>; 89 qcom,acc = <&acc3>; 90 qcom,saw = <&saw3>; 91 #cooling-cells = <2>; 92 }; 93 94 l2: l2-cache { 95 compatible = "cache"; 96 cache-level = <2>; 97 cache-unified; 98 }; 99 }; 100 101 firmware { 102 scm { 103 compatible = "qcom,scm-msm8226", "qcom,scm"; 104 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 105 clock-names = "core", "bus", "iface"; 106 }; 107 }; 108 109 memory@0 { 110 device_type = "memory"; 111 reg = <0x0 0x0>; 112 }; 113 114 cpu_opp_table: opp-table-cpu { 115 compatible = "operating-points-v2"; 116 opp-shared; 117 118 opp-300000000 { 119 opp-hz = /bits/ 64 <300000000>; 120 }; 121 122 opp-384000000 { 123 opp-hz = /bits/ 64 <384000000>; 124 }; 125 126 opp-600000000 { 127 opp-hz = /bits/ 64 <600000000>; 128 }; 129 130 opp-787200000 { 131 opp-hz = /bits/ 64 <787200000>; 132 }; 133 134 /* Higher CPU frequencies need speedbin support */ 135 }; 136 137 pmu { 138 compatible = "arm,cortex-a7-pmu"; 139 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 140 IRQ_TYPE_LEVEL_HIGH)>; 141 }; 142 143 rpm: remoteproc { 144 compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc"; 145 146 master-stats { 147 compatible = "qcom,rpm-master-stats"; 148 qcom,rpm-msg-ram = <&apss_master_stats>, 149 <&mpss_master_stats>, 150 <&lpss_master_stats>, 151 <&pronto_master_stats>; 152 qcom,master-names = "APSS", 153 "MPSS", 154 "LPSS", 155 "PRONTO"; 156 }; 157 158 smd-edge { 159 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 160 mboxes = <&apcs 0>; 161 qcom,smd-edge = <15>; 162 163 rpm_requests: rpm-requests { 164 compatible = "qcom,rpm-msm8226", "qcom,smd-rpm"; 165 qcom,smd-channels = "rpm_requests"; 166 167 rpmcc: clock-controller { 168 compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc"; 169 #clock-cells = <1>; 170 clocks = <&xo_board>; 171 clock-names = "xo"; 172 }; 173 174 rpmpd: power-controller { 175 compatible = "qcom,msm8226-rpmpd"; 176 #power-domain-cells = <1>; 177 operating-points-v2 = <&rpmpd_opp_table>; 178 179 rpmpd_opp_table: opp-table { 180 compatible = "operating-points-v2"; 181 182 rpmpd_opp_ret: opp1 { 183 opp-level = <1>; 184 }; 185 rpmpd_opp_svs_krait: opp2 { 186 opp-level = <2>; 187 }; 188 rpmpd_opp_svs_soc: opp3 { 189 opp-level = <3>; 190 }; 191 rpmpd_opp_nom: opp4 { 192 opp-level = <4>; 193 }; 194 rpmpd_opp_turbo: opp5 { 195 opp-level = <5>; 196 }; 197 rpmpd_opp_super_turbo: opp6 { 198 opp-level = <6>; 199 }; 200 }; 201 }; 202 }; 203 }; 204 }; 205 206 reserved-memory { 207 #address-cells = <1>; 208 #size-cells = <1>; 209 ranges; 210 211 smem_region: smem@3000000 { 212 reg = <0x3000000 0x100000>; 213 no-map; 214 }; 215 216 adsp_region: adsp@dc00000 { 217 reg = <0x0dc00000 0x1900000>; 218 no-map; 219 }; 220 }; 221 222 smem { 223 compatible = "qcom,smem"; 224 225 memory-region = <&smem_region>; 226 qcom,rpm-msg-ram = <&rpm_msg_ram>; 227 228 hwlocks = <&tcsr_mutex 3>; 229 }; 230 231 smp2p-adsp { 232 compatible = "qcom,smp2p"; 233 qcom,smem = <443>, <429>; 234 235 interrupt-parent = <&intc>; 236 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 237 238 mboxes = <&apcs 10>; 239 240 qcom,local-pid = <0>; 241 qcom,remote-pid = <2>; 242 243 adsp_smp2p_out: master-kernel { 244 qcom,entry-name = "master-kernel"; 245 #qcom,smem-state-cells = <1>; 246 }; 247 248 adsp_smp2p_in: slave-kernel { 249 qcom,entry-name = "slave-kernel"; 250 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 }; 254 }; 255 256 soc: soc { 257 compatible = "simple-bus"; 258 #address-cells = <1>; 259 #size-cells = <1>; 260 ranges; 261 262 intc: interrupt-controller@f9000000 { 263 compatible = "qcom,msm-qgic2"; 264 reg = <0xf9000000 0x1000>, 265 <0xf9002000 0x1000>; 266 interrupt-controller; 267 #interrupt-cells = <3>; 268 }; 269 270 apcs: mailbox@f9011000 { 271 compatible = "qcom,msm8226-apcs-kpss-global", 272 "qcom,msm8916-apcs-kpss-global", "syscon"; 273 reg = <0xf9011000 0x1000>; 274 #mbox-cells = <1>; 275 clocks = <&a7pll>, <&gcc GPLL0_VOTE>; 276 clock-names = "pll", "aux"; 277 #clock-cells = <0>; 278 }; 279 280 a7pll: clock@f9016000 { 281 compatible = "qcom,msm8226-a7pll"; 282 reg = <0xf9016000 0x40>; 283 #clock-cells = <0>; 284 clocks = <&xo_board>; 285 clock-names = "xo"; 286 operating-points-v2 = <&a7pll_opp_table>; 287 288 a7pll_opp_table: opp-table { 289 compatible = "operating-points-v2"; 290 291 opp-768000000 { 292 opp-hz = /bits/ 64 <768000000>; 293 }; 294 295 opp-787200000 { 296 opp-hz = /bits/ 64 <787200000>; 297 }; 298 299 opp-998400000 { 300 opp-hz = /bits/ 64 <998400000>; 301 }; 302 303 opp-1094400000 { 304 opp-hz = /bits/ 64 <1094400000>; 305 }; 306 307 opp-1190400000 { 308 opp-hz = /bits/ 64 <1190400000>; 309 }; 310 311 opp-1305600000 { 312 opp-hz = /bits/ 64 <1305600000>; 313 }; 314 315 opp-1344000000 { 316 opp-hz = /bits/ 64 <1344000000>; 317 }; 318 319 opp-1401600000 { 320 opp-hz = /bits/ 64 <1401600000>; 321 }; 322 323 opp-1497600000 { 324 opp-hz = /bits/ 64 <1497600000>; 325 }; 326 327 opp-1593600000 { 328 opp-hz = /bits/ 64 <1593600000>; 329 }; 330 331 opp-1689600000 { 332 opp-hz = /bits/ 64 <1689600000>; 333 }; 334 335 opp-1785600000 { 336 opp-hz = /bits/ 64 <1785600000>; 337 }; 338 }; 339 }; 340 341 saw_l2: power-manager@f9012000 { 342 compatible = "qcom,msm8226-saw2-v2.1-l2", "qcom,saw2"; 343 reg = <0xf9012000 0x1000>; 344 }; 345 346 watchdog@f9017000 { 347 compatible = "qcom,apss-wdt-msm8226", "qcom,kpss-wdt"; 348 reg = <0xf9017000 0x1000>; 349 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 350 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 351 clocks = <&sleep_clk>; 352 }; 353 354 timer@f9020000 { 355 compatible = "arm,armv7-timer-mem"; 356 reg = <0xf9020000 0x1000>; 357 #address-cells = <1>; 358 #size-cells = <1>; 359 ranges; 360 361 frame@f9021000 { 362 frame-number = <0>; 363 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 365 reg = <0xf9021000 0x1000>, 366 <0xf9022000 0x1000>; 367 }; 368 369 frame@f9023000 { 370 frame-number = <1>; 371 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 372 reg = <0xf9023000 0x1000>; 373 status = "disabled"; 374 }; 375 376 frame@f9024000 { 377 frame-number = <2>; 378 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 379 reg = <0xf9024000 0x1000>; 380 status = "disabled"; 381 }; 382 383 frame@f9025000 { 384 frame-number = <3>; 385 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 386 reg = <0xf9025000 0x1000>; 387 status = "disabled"; 388 }; 389 390 frame@f9026000 { 391 frame-number = <4>; 392 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 393 reg = <0xf9026000 0x1000>; 394 status = "disabled"; 395 }; 396 397 frame@f9027000 { 398 frame-number = <5>; 399 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 400 reg = <0xf9027000 0x1000>; 401 status = "disabled"; 402 }; 403 404 frame@f9028000 { 405 frame-number = <6>; 406 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 407 reg = <0xf9028000 0x1000>; 408 status = "disabled"; 409 }; 410 }; 411 412 acc0: power-manager@f9088000 { 413 compatible = "qcom,kpss-acc-v2"; 414 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 415 }; 416 417 saw0: power-manager@f9089000 { 418 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; 419 reg = <0xf9089000 0x1000>; 420 }; 421 422 acc1: power-manager@f9098000 { 423 compatible = "qcom,kpss-acc-v2"; 424 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 425 }; 426 427 saw1: power-manager@f9099000 { 428 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; 429 reg = <0xf9099000 0x1000>; 430 }; 431 432 acc2: power-manager@f90a8000 { 433 compatible = "qcom,kpss-acc-v2"; 434 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 435 }; 436 437 saw2: power-manager@f90a9000 { 438 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; 439 reg = <0xf90a9000 0x1000>; 440 }; 441 442 acc3: power-manager@f90b8000 { 443 compatible = "qcom,kpss-acc-v2"; 444 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 445 }; 446 447 saw3: power-manager@f90b9000 { 448 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; 449 reg = <0xf90b9000 0x1000>; 450 }; 451 452 sdhc_1: mmc@f9824900 { 453 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 454 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 455 reg-names = "hc", "core"; 456 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 458 interrupt-names = "hc_irq", "pwr_irq"; 459 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 460 <&gcc GCC_SDCC1_APPS_CLK>, 461 <&rpmcc RPM_SMD_XO_CLK_SRC>; 462 clock-names = "iface", "core", "xo"; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&sdhc1_default_state>; 465 status = "disabled"; 466 }; 467 468 sdhc_3: mmc@f9864900 { 469 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 470 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 471 reg-names = "hc", "core"; 472 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 474 interrupt-names = "hc_irq", "pwr_irq"; 475 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 476 <&gcc GCC_SDCC3_APPS_CLK>, 477 <&rpmcc RPM_SMD_XO_CLK_SRC>; 478 clock-names = "iface", "core", "xo"; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&sdhc3_default_state>; 481 status = "disabled"; 482 }; 483 484 sdhc_2: mmc@f98a4900 { 485 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 486 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 487 reg-names = "hc", "core"; 488 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 490 interrupt-names = "hc_irq", "pwr_irq"; 491 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 492 <&gcc GCC_SDCC2_APPS_CLK>, 493 <&rpmcc RPM_SMD_XO_CLK_SRC>; 494 clock-names = "iface", "core", "xo"; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&sdhc2_default_state>; 497 status = "disabled"; 498 }; 499 500 blsp1_uart1: serial@f991d000 { 501 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 502 reg = <0xf991d000 0x1000>; 503 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 505 clock-names = "core", "iface"; 506 status = "disabled"; 507 }; 508 509 blsp1_uart2: serial@f991e000 { 510 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 511 reg = <0xf991e000 0x1000>; 512 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 514 <&gcc GCC_BLSP1_AHB_CLK>; 515 clock-names = "core", 516 "iface"; 517 status = "disabled"; 518 }; 519 520 blsp1_uart3: serial@f991f000 { 521 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 522 reg = <0xf991f000 0x1000>; 523 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 525 clock-names = "core", "iface"; 526 status = "disabled"; 527 }; 528 529 blsp1_uart4: serial@f9920000 { 530 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 531 reg = <0xf9920000 0x1000>; 532 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 534 clock-names = "core", "iface"; 535 status = "disabled"; 536 }; 537 538 blsp1_i2c1: i2c@f9923000 { 539 compatible = "qcom,i2c-qup-v2.1.1"; 540 reg = <0xf9923000 0x1000>; 541 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 543 clock-names = "core", "iface"; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&blsp1_i2c1_pins>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 status = "disabled"; 549 }; 550 551 blsp1_i2c2: i2c@f9924000 { 552 compatible = "qcom,i2c-qup-v2.1.1"; 553 reg = <0xf9924000 0x1000>; 554 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 556 clock-names = "core", "iface"; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&blsp1_i2c2_pins>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 status = "disabled"; 562 }; 563 564 blsp1_i2c3: i2c@f9925000 { 565 compatible = "qcom,i2c-qup-v2.1.1"; 566 reg = <0xf9925000 0x1000>; 567 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 569 clock-names = "core", "iface"; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&blsp1_i2c3_pins>; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 status = "disabled"; 575 }; 576 577 blsp1_i2c4: i2c@f9926000 { 578 compatible = "qcom,i2c-qup-v2.1.1"; 579 reg = <0xf9926000 0x1000>; 580 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 582 clock-names = "core", "iface"; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&blsp1_i2c4_pins>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 status = "disabled"; 588 }; 589 590 blsp1_i2c5: i2c@f9927000 { 591 compatible = "qcom,i2c-qup-v2.1.1"; 592 reg = <0xf9927000 0x1000>; 593 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 595 clock-names = "core", "iface"; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&blsp1_i2c5_pins>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 status = "disabled"; 601 }; 602 603 blsp1_i2c6: i2c@f9928000 { 604 compatible = "qcom,i2c-qup-v2.1.1"; 605 reg = <0xf9928000 0x1000>; 606 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 608 <&gcc GCC_BLSP1_AHB_CLK>; 609 clock-names = "core", 610 "iface"; 611 pinctrl-0 = <&blsp1_i2c6_pins>; 612 pinctrl-names = "default"; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 status = "disabled"; 616 }; 617 618 usb: usb@f9a55000 { 619 compatible = "qcom,ci-hdrc"; 620 reg = <0xf9a55000 0x200>, 621 <0xf9a55200 0x200>; 622 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 624 <&gcc GCC_USB_HS_SYSTEM_CLK>; 625 clock-names = "iface", "core"; 626 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 627 assigned-clock-rates = <75000000>; 628 resets = <&gcc GCC_USB_HS_BCR>; 629 reset-names = "core"; 630 phy_type = "ulpi"; 631 dr_mode = "otg"; 632 hnp-disable; 633 srp-disable; 634 adp-disable; 635 ahb-burst-config = <0>; 636 phy-names = "usb-phy"; 637 phys = <&usb_hs_phy>; 638 status = "disabled"; 639 #reset-cells = <1>; 640 641 ulpi { 642 usb_hs_phy: phy { 643 compatible = "qcom,usb-hs-phy-msm8226", 644 "qcom,usb-hs-phy"; 645 #phy-cells = <0>; 646 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 647 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 648 clock-names = "ref", "sleep"; 649 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 650 reset-names = "phy", "por"; 651 qcom,init-seq = /bits/ 8 <0x0 0x44 652 0x1 0x68 0x2 0x24 0x3 0x13>; 653 }; 654 }; 655 }; 656 657 rng@f9bff000 { 658 compatible = "qcom,prng"; 659 reg = <0xf9bff000 0x200>; 660 clocks = <&gcc GCC_PRNG_AHB_CLK>; 661 clock-names = "core"; 662 }; 663 664 sram@fc190000 { 665 compatible = "qcom,msm8226-rpm-stats"; 666 reg = <0xfc190000 0x10000>; 667 }; 668 669 gcc: clock-controller@fc400000 { 670 compatible = "qcom,gcc-msm8226"; 671 reg = <0xfc400000 0x4000>; 672 #clock-cells = <1>; 673 #reset-cells = <1>; 674 #power-domain-cells = <1>; 675 676 clocks = <&xo_board>, 677 <&sleep_clk>; 678 clock-names = "xo", 679 "sleep_clk"; 680 }; 681 682 rpm_msg_ram: sram@fc428000 { 683 compatible = "qcom,rpm-msg-ram"; 684 reg = <0xfc428000 0x4000>; 685 686 #address-cells = <1>; 687 #size-cells = <1>; 688 ranges = <0 0xfc428000 0x4000>; 689 690 apss_master_stats: sram@150 { 691 reg = <0x150 0x14>; 692 }; 693 694 mpss_master_stats: sram@b50 { 695 reg = <0xb50 0x14>; 696 }; 697 698 lpss_master_stats: sram@1550 { 699 reg = <0x1550 0x14>; 700 }; 701 702 pronto_master_stats: sram@1f50 { 703 reg = <0x1f50 0x14>; 704 }; 705 }; 706 707 tsens: thermal-sensor@fc4a9000 { 708 compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1"; 709 reg = <0xfc4a9000 0x1000>, /* TM */ 710 <0xfc4a8000 0x1000>; /* SROT */ 711 nvmem-cells = <&tsens_mode>, 712 <&tsens_base1>, <&tsens_base2>, 713 <&tsens_s0_p1>, <&tsens_s0_p2>, 714 <&tsens_s1_p1>, <&tsens_s1_p2>, 715 <&tsens_s2_p1>, <&tsens_s2_p2>, 716 <&tsens_s3_p1>, <&tsens_s3_p2>, 717 <&tsens_s4_p1>, <&tsens_s4_p2>, 718 <&tsens_s5_p1>, <&tsens_s5_p2>, 719 <&tsens_s6_p1>, <&tsens_s6_p2>; 720 nvmem-cell-names = "mode", 721 "base1", "base2", 722 "s0_p1", "s0_p2", 723 "s1_p1", "s1_p2", 724 "s2_p1", "s2_p2", 725 "s3_p1", "s3_p2", 726 "s4_p1", "s4_p2", 727 "s5_p1", "s5_p2", 728 "s6_p1", "s6_p2"; 729 #qcom,sensors = <6>; 730 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 731 interrupt-names = "uplow"; 732 #thermal-sensor-cells = <1>; 733 }; 734 735 restart@fc4ab000 { 736 compatible = "qcom,pshold"; 737 reg = <0xfc4ab000 0x4>; 738 }; 739 740 qfprom: efuse@fc4bc000 { 741 compatible = "qcom,msm8226-qfprom", "qcom,qfprom"; 742 reg = <0xfc4bc000 0x1000>; 743 #address-cells = <1>; 744 #size-cells = <1>; 745 746 tsens_base1: base1@1c1 { 747 reg = <0x1c1 0x2>; 748 bits = <5 8>; 749 }; 750 751 tsens_s0_p1: s0-p1@1c2 { 752 reg = <0x1c2 0x2>; 753 bits = <5 6>; 754 }; 755 756 tsens_s1_p1: s1-p1@1c4 { 757 reg = <0x1c4 0x1>; 758 bits = <0 6>; 759 }; 760 761 tsens_s2_p1: s2-p1@1c4 { 762 reg = <0x1c4 0x2>; 763 bits = <6 6>; 764 }; 765 766 tsens_s3_p1: s3-p1@1c5 { 767 reg = <0x1c5 0x2>; 768 bits = <4 6>; 769 }; 770 771 tsens_s4_p1: s4-p1@1c6 { 772 reg = <0x1c6 0x1>; 773 bits = <2 6>; 774 }; 775 776 tsens_s5_p1: s5-p1@1c7 { 777 reg = <0x1c7 0x1>; 778 bits = <0 6>; 779 }; 780 781 tsens_s6_p1: s6-p1@1ca { 782 reg = <0x1ca 0x2>; 783 bits = <4 6>; 784 }; 785 786 tsens_base2: base2@1cc { 787 reg = <0x1cc 0x1>; 788 bits = <0 8>; 789 }; 790 791 tsens_s0_p2: s0-p2@1cd { 792 reg = <0x1cd 0x1>; 793 bits = <0 6>; 794 }; 795 796 tsens_s1_p2: s1-p2@1cd { 797 reg = <0x1cd 0x2>; 798 bits = <6 6>; 799 }; 800 801 tsens_s2_p2: s2-p2@1ce { 802 reg = <0x1ce 0x2>; 803 bits = <4 6>; 804 }; 805 806 tsens_s3_p2: s3-p2@1cf { 807 reg = <0x1cf 0x1>; 808 bits = <2 6>; 809 }; 810 811 tsens_s4_p2: s4-p2@446 { 812 reg = <0x446 0x2>; 813 bits = <4 6>; 814 }; 815 816 tsens_s5_p2: s5-p2@447 { 817 reg = <0x447 0x1>; 818 bits = <2 6>; 819 }; 820 821 tsens_s6_p2: s6-p2@44e { 822 reg = <0x44e 0x1>; 823 bits = <1 6>; 824 }; 825 826 tsens_mode: mode@44f { 827 reg = <0x44f 0x1>; 828 bits = <5 3>; 829 }; 830 }; 831 832 spmi_bus: spmi@fc4cf000 { 833 compatible = "qcom,spmi-pmic-arb"; 834 reg-names = "core", "intr", "cnfg"; 835 reg = <0xfc4cf000 0x1000>, 836 <0xfc4cb000 0x1000>, 837 <0xfc4ca000 0x1000>; 838 interrupt-names = "periph_irq"; 839 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 840 qcom,ee = <0>; 841 qcom,channel = <0>; 842 #address-cells = <2>; 843 #size-cells = <0>; 844 interrupt-controller; 845 #interrupt-cells = <4>; 846 }; 847 848 tcsr_mutex: hwlock@fd484000 { 849 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; 850 reg = <0xfd484000 0x1000>; 851 #hwlock-cells = <1>; 852 }; 853 854 tlmm: pinctrl@fd510000 { 855 compatible = "qcom,msm8226-pinctrl"; 856 reg = <0xfd510000 0x4000>; 857 gpio-controller; 858 #gpio-cells = <2>; 859 gpio-ranges = <&tlmm 0 0 117>; 860 interrupt-controller; 861 #interrupt-cells = <2>; 862 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 863 864 blsp1_i2c1_pins: blsp1-i2c1-state { 865 pins = "gpio2", "gpio3"; 866 function = "blsp_i2c1"; 867 drive-strength = <2>; 868 bias-disable; 869 }; 870 871 blsp1_i2c2_pins: blsp1-i2c2-state { 872 pins = "gpio6", "gpio7"; 873 function = "blsp_i2c2"; 874 drive-strength = <2>; 875 bias-disable; 876 }; 877 878 blsp1_i2c3_pins: blsp1-i2c3-state { 879 pins = "gpio10", "gpio11"; 880 function = "blsp_i2c3"; 881 drive-strength = <2>; 882 bias-disable; 883 }; 884 885 blsp1_i2c4_pins: blsp1-i2c4-state { 886 pins = "gpio14", "gpio15"; 887 function = "blsp_i2c4"; 888 drive-strength = <2>; 889 bias-disable; 890 }; 891 892 blsp1_i2c5_pins: blsp1-i2c5-state { 893 pins = "gpio18", "gpio19"; 894 function = "blsp_i2c5"; 895 drive-strength = <2>; 896 bias-disable; 897 }; 898 899 blsp1_i2c6_pins: blsp1-i2c6-state { 900 pins = "gpio22", "gpio23"; 901 function = "blsp_i2c6"; 902 drive-strength = <2>; 903 bias-disable; 904 }; 905 906 cci_default: cci-default-state { 907 pins = "gpio29", "gpio30"; 908 function = "cci_i2c0"; 909 910 drive-strength = <2>; 911 bias-disable; 912 }; 913 914 cci_sleep: cci-sleep-state { 915 pins = "gpio29", "gpio30"; 916 function = "gpio"; 917 918 drive-strength = <2>; 919 bias-disable; 920 }; 921 922 sdhc1_default_state: sdhc1-default-state { 923 clk-pins { 924 pins = "sdc1_clk"; 925 drive-strength = <10>; 926 bias-disable; 927 }; 928 929 cmd-data-pins { 930 pins = "sdc1_cmd", "sdc1_data"; 931 drive-strength = <10>; 932 bias-pull-up; 933 }; 934 }; 935 936 sdhc2_default_state: sdhc2-default-state { 937 clk-pins { 938 pins = "sdc2_clk"; 939 drive-strength = <10>; 940 bias-disable; 941 }; 942 943 cmd-data-pins { 944 pins = "sdc2_cmd", "sdc2_data"; 945 drive-strength = <10>; 946 bias-pull-up; 947 }; 948 }; 949 950 sdhc3_default_state: sdhc3-default-state { 951 clk-pins { 952 pins = "gpio44"; 953 function = "sdc3"; 954 drive-strength = <8>; 955 bias-disable; 956 }; 957 958 cmd-pins { 959 pins = "gpio43"; 960 function = "sdc3"; 961 drive-strength = <8>; 962 bias-pull-up; 963 }; 964 965 data-pins { 966 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 967 function = "sdc3"; 968 drive-strength = <8>; 969 bias-pull-up; 970 }; 971 }; 972 }; 973 974 mmcc: clock-controller@fd8c0000 { 975 compatible = "qcom,mmcc-msm8226"; 976 reg = <0xfd8c0000 0x6000>; 977 #clock-cells = <1>; 978 #reset-cells = <1>; 979 #power-domain-cells = <1>; 980 981 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 982 <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 983 <&gcc GPLL0_VOTE>, 984 <&gcc GPLL1_VOTE>, 985 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 986 <&mdss_dsi0_phy 1>, 987 <&mdss_dsi0_phy 0>; 988 clock-names = "xo", 989 "mmss_gpll0_vote", 990 "gpll0_vote", 991 "gpll1_vote", 992 "gfx3d_clk_src", 993 "dsi0pll", 994 "dsi0pllbyte"; 995 }; 996 997 mdss: display-subsystem@fd900000 { 998 compatible = "qcom,mdss"; 999 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 1000 reg-names = "mdss_phys", "vbif_phys"; 1001 1002 power-domains = <&mmcc MDSS_GDSC>; 1003 1004 clocks = <&mmcc MDSS_AHB_CLK>, 1005 <&mmcc MDSS_AXI_CLK>, 1006 <&mmcc MDSS_VSYNC_CLK>; 1007 clock-names = "iface", 1008 "bus", 1009 "vsync"; 1010 1011 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1012 1013 interrupt-controller; 1014 #interrupt-cells = <1>; 1015 1016 #address-cells = <1>; 1017 #size-cells = <1>; 1018 ranges; 1019 1020 status = "disabled"; 1021 1022 mdss_mdp: display-controller@fd900000 { 1023 compatible = "qcom,msm8226-mdp5", "qcom,mdp5"; 1024 reg = <0xfd900100 0x22000>; 1025 reg-names = "mdp_phys"; 1026 1027 interrupt-parent = <&mdss>; 1028 interrupts = <0>; 1029 1030 clocks = <&mmcc MDSS_AHB_CLK>, 1031 <&mmcc MDSS_AXI_CLK>, 1032 <&mmcc MDSS_MDP_CLK>, 1033 <&mmcc MDSS_VSYNC_CLK>; 1034 clock-names = "iface", 1035 "bus", 1036 "core", 1037 "vsync"; 1038 1039 ports { 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 1043 port@0 { 1044 reg = <0>; 1045 mdss_mdp_intf1_out: endpoint { 1046 remote-endpoint = <&mdss_dsi0_in>; 1047 }; 1048 }; 1049 }; 1050 }; 1051 1052 mdss_dsi0: dsi@fd922800 { 1053 compatible = "qcom,msm8226-dsi-ctrl", 1054 "qcom,mdss-dsi-ctrl"; 1055 reg = <0xfd922800 0x1f8>; 1056 reg-names = "dsi_ctrl"; 1057 1058 interrupt-parent = <&mdss>; 1059 interrupts = <4>; 1060 1061 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1062 <&mmcc PCLK0_CLK_SRC>; 1063 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1064 <&mdss_dsi0_phy 1>; 1065 1066 clocks = <&mmcc MDSS_MDP_CLK>, 1067 <&mmcc MDSS_AHB_CLK>, 1068 <&mmcc MDSS_AXI_CLK>, 1069 <&mmcc MDSS_BYTE0_CLK>, 1070 <&mmcc MDSS_PCLK0_CLK>, 1071 <&mmcc MDSS_ESC0_CLK>, 1072 <&mmcc MMSS_MISC_AHB_CLK>; 1073 clock-names = "mdp_core", 1074 "iface", 1075 "bus", 1076 "byte", 1077 "pixel", 1078 "core", 1079 "core_mmss"; 1080 1081 phys = <&mdss_dsi0_phy>; 1082 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 1086 ports { 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 1090 port@0 { 1091 reg = <0>; 1092 mdss_dsi0_in: endpoint { 1093 remote-endpoint = <&mdss_mdp_intf1_out>; 1094 }; 1095 }; 1096 1097 port@1 { 1098 reg = <1>; 1099 mdss_dsi0_out: endpoint { 1100 }; 1101 }; 1102 }; 1103 }; 1104 1105 mdss_dsi0_phy: phy@fd922a00 { 1106 compatible = "qcom,dsi-phy-28nm-8226"; 1107 reg = <0xfd922a00 0xd4>, 1108 <0xfd922b00 0x280>, 1109 <0xfd922d80 0x30>; 1110 reg-names = "dsi_pll", 1111 "dsi_phy", 1112 "dsi_phy_regulator"; 1113 1114 #clock-cells = <1>; 1115 #phy-cells = <0>; 1116 1117 clocks = <&mmcc MDSS_AHB_CLK>, 1118 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1119 clock-names = "iface", 1120 "ref"; 1121 }; 1122 }; 1123 1124 cci: cci@fda0c000 { 1125 compatible = "qcom,msm8226-cci"; 1126 reg = <0xfda0c000 0x1000>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1130 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1131 <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 1132 <&mmcc CAMSS_CCI_CCI_CLK>; 1133 clock-names = "camss_top_ahb", 1134 "cci_ahb", 1135 "cci"; 1136 1137 pinctrl-names = "default", "sleep"; 1138 pinctrl-0 = <&cci_default>; 1139 pinctrl-1 = <&cci_sleep>; 1140 1141 status = "disabled"; 1142 1143 cci_i2c0: i2c-bus@0 { 1144 reg = <0>; 1145 clock-frequency = <400000>; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 }; 1149 }; 1150 1151 gpu: gpu@fdb00000 { 1152 compatible = "qcom,adreno-305.18", "qcom,adreno"; 1153 reg = <0xfdb00000 0x10000>; 1154 reg-names = "kgsl_3d0_reg_memory"; 1155 1156 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1157 interrupt-names = "kgsl_3d0_irq"; 1158 1159 clocks = <&mmcc OXILI_GFX3D_CLK>, 1160 <&mmcc OXILICX_AHB_CLK>, 1161 <&mmcc OXILICX_AXI_CLK>; 1162 clock-names = "core", "iface", "mem_iface"; 1163 1164 sram = <&gmu_sram>; 1165 power-domains = <&mmcc OXILICX_GDSC>; 1166 operating-points-v2 = <&gpu_opp_table>; 1167 1168 status = "disabled"; 1169 1170 gpu_opp_table: opp-table { 1171 compatible = "operating-points-v2"; 1172 1173 opp-450000000 { 1174 opp-hz = /bits/ 64 <450000000>; 1175 }; 1176 1177 opp-320000000 { 1178 opp-hz = /bits/ 64 <320000000>; 1179 }; 1180 1181 opp-200000000 { 1182 opp-hz = /bits/ 64 <200000000>; 1183 }; 1184 1185 opp-19000000 { 1186 opp-hz = /bits/ 64 <19000000>; 1187 }; 1188 }; 1189 }; 1190 1191 sram@fdd00000 { 1192 compatible = "qcom,msm8226-ocmem"; 1193 reg = <0xfdd00000 0x2000>, 1194 <0xfec00000 0x20000>; 1195 reg-names = "ctrl", "mem"; 1196 ranges = <0 0xfec00000 0x20000>; 1197 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>; 1198 clock-names = "core"; 1199 1200 #address-cells = <1>; 1201 #size-cells = <1>; 1202 1203 gmu_sram: gmu-sram@0 { 1204 reg = <0x0 0x20000>; 1205 }; 1206 }; 1207 1208 adsp: remoteproc@fe200000 { 1209 compatible = "qcom,msm8226-adsp-pil"; 1210 reg = <0xfe200000 0x100>; 1211 1212 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 1213 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1214 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1215 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1216 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1217 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1218 1219 power-domains = <&rpmpd MSM8226_VDDCX>; 1220 power-domain-names = "cx"; 1221 1222 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1223 clock-names = "xo"; 1224 1225 memory-region = <&adsp_region>; 1226 1227 qcom,smem-states = <&adsp_smp2p_out 0>; 1228 qcom,smem-state-names = "stop"; 1229 1230 status = "disabled"; 1231 1232 smd-edge { 1233 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 1234 1235 mboxes = <&apcs 8>; 1236 qcom,smd-edge = <1>; 1237 1238 label = "lpass"; 1239 }; 1240 }; 1241 1242 sram@fe805000 { 1243 compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; 1244 reg = <0xfe805000 0x1000>; 1245 1246 reboot-mode { 1247 compatible = "syscon-reboot-mode"; 1248 offset = <0x65c>; 1249 1250 mode-bootloader = <0x77665500>; 1251 mode-normal = <0x77665501>; 1252 mode-recovery = <0x77665502>; 1253 }; 1254 }; 1255 }; 1256 1257 thermal-zones { 1258 cpu0-thermal { 1259 polling-delay-passive = <250>; 1260 polling-delay = <1000>; 1261 1262 thermal-sensors = <&tsens 5>; 1263 1264 cooling-maps { 1265 map0 { 1266 trip = <&cpu_alert0>; 1267 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1268 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1269 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1270 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1271 }; 1272 }; 1273 1274 trips { 1275 cpu_alert0: trip0 { 1276 temperature = <75000>; 1277 hysteresis = <2000>; 1278 type = "passive"; 1279 }; 1280 1281 cpu_crit0: trip1 { 1282 temperature = <110000>; 1283 hysteresis = <2000>; 1284 type = "critical"; 1285 }; 1286 }; 1287 }; 1288 1289 cpu1-thermal { 1290 polling-delay-passive = <250>; 1291 polling-delay = <1000>; 1292 1293 thermal-sensors = <&tsens 2>; 1294 1295 cooling-maps { 1296 map0 { 1297 trip = <&cpu_alert1>; 1298 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1299 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1300 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1301 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1302 }; 1303 }; 1304 1305 trips { 1306 cpu_alert1: trip0 { 1307 temperature = <75000>; 1308 hysteresis = <2000>; 1309 type = "passive"; 1310 }; 1311 1312 cpu_crit1: trip1 { 1313 temperature = <110000>; 1314 hysteresis = <2000>; 1315 type = "critical"; 1316 }; 1317 }; 1318 }; 1319 }; 1320 1321 timer { 1322 compatible = "arm,armv7-timer"; 1323 interrupts = <GIC_PPI 2 1324 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 1325 <GIC_PPI 3 1326 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 1327 <GIC_PPI 4 1328 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 1329 <GIC_PPI 1 1330 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; 1331 }; 1332}; 1333