1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 NXP Semiconductors. 4 * Author: Fabio Estevam <fabio.estevam@nxp.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/input/input.h> 10#include "imx7s.dtsi" 11 12/ { 13 model = "Element14 Warp i.MX7 Board"; 14 compatible = "element14,imx7s-warp", "fsl,imx7s"; 15 16 memory@80000000 { 17 device_type = "memory"; 18 reg = <0x80000000 0x20000000>; 19 }; 20 21 gpio-keys { 22 compatible = "gpio-keys"; 23 pinctrl-0 = <&pinctrl_gpio>; 24 autorepeat; 25 26 back { 27 label = "Back"; 28 gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 29 linux,code = <KEY_BACK>; 30 wakeup-source; 31 }; 32 }; 33 34 reg_peri_3p15v: regulator-peri-3p15v { 35 compatible = "regulator-fixed"; 36 regulator-name = "peri_3p15v_reg"; 37 regulator-min-microvolt = <3150000>; 38 regulator-max-microvolt = <3150000>; 39 regulator-always-on; 40 }; 41 42 sdio_pwrseq: sdio-pwrseq { 43 compatible = "mmc-pwrseq-simple"; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_brcm_reg>; 46 post-power-on-delay-ms = <200>; 47 reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; 48 }; 49 50 sound { 51 compatible = "simple-audio-card"; 52 simple-audio-card,name = "imx7-sgtl5000"; 53 simple-audio-card,format = "i2s"; 54 simple-audio-card,bitclock-master = <&dailink_master>; 55 simple-audio-card,frame-master = <&dailink_master>; 56 simple-audio-card,cpu { 57 sound-dai = <&sai1>; 58 }; 59 60 dailink_master: simple-audio-card,codec { 61 sound-dai = <&codec>; 62 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; 63 }; 64 }; 65}; 66 67&clks { 68 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 69 assigned-clock-rates = <884736000>; 70}; 71 72&csi { 73 status = "okay"; 74}; 75 76&i2c1 { 77 pinctrl-names = "default"; 78 pinctrl-0 = <&pinctrl_i2c1>; 79 status = "okay"; 80 81 pmic: pmic@8 { 82 compatible = "fsl,pfuze3000"; 83 reg = <0x08>; 84 85 regulators { 86 sw1a_reg: sw1a { 87 regulator-min-microvolt = <700000>; 88 regulator-max-microvolt = <1475000>; 89 regulator-boot-on; 90 regulator-always-on; 91 regulator-ramp-delay = <6250>; 92 }; 93 94 /* use sw1c_reg to align with pfuze100/pfuze200 */ 95 sw1c_reg: sw1b { 96 regulator-min-microvolt = <700000>; 97 regulator-max-microvolt = <1475000>; 98 regulator-boot-on; 99 regulator-always-on; 100 regulator-ramp-delay = <6250>; 101 }; 102 103 sw2_reg: sw2 { 104 regulator-min-microvolt = <1500000>; 105 regulator-max-microvolt = <1850000>; 106 regulator-boot-on; 107 regulator-always-on; 108 }; 109 110 sw3a_reg: sw3 { 111 regulator-min-microvolt = <900000>; 112 regulator-max-microvolt = <1650000>; 113 regulator-boot-on; 114 regulator-always-on; 115 }; 116 117 swbst_reg: swbst { 118 regulator-min-microvolt = <5000000>; 119 regulator-max-microvolt = <5150000>; 120 regulator-boot-on; 121 regulator-always-on; 122 }; 123 124 snvs_reg: vsnvs { 125 regulator-min-microvolt = <1000000>; 126 regulator-max-microvolt = <3000000>; 127 regulator-boot-on; 128 regulator-always-on; 129 }; 130 131 vref_reg: vrefddr { 132 regulator-boot-on; 133 regulator-always-on; 134 }; 135 136 vgen1_reg: vldo1 { 137 regulator-min-microvolt = <1800000>; 138 regulator-max-microvolt = <3300000>; 139 regulator-always-on; 140 }; 141 142 vgen2_reg: vldo2 { 143 regulator-min-microvolt = <800000>; 144 regulator-max-microvolt = <1550000>; 145 }; 146 147 vgen3_reg: vccsd { 148 regulator-min-microvolt = <2850000>; 149 regulator-max-microvolt = <3300000>; 150 regulator-always-on; 151 }; 152 153 vgen4_reg: v33 { 154 regulator-min-microvolt = <2850000>; 155 regulator-max-microvolt = <3300000>; 156 regulator-always-on; 157 }; 158 159 vgen5_reg: vldo3 { 160 regulator-min-microvolt = <1800000>; 161 regulator-max-microvolt = <3300000>; 162 regulator-always-on; 163 }; 164 165 vgen6_reg: vldo4 { 166 regulator-min-microvolt = <1800000>; 167 regulator-max-microvolt = <3300000>; 168 regulator-always-on; 169 }; 170 }; 171 }; 172}; 173 174&i2c2 { 175 clock-frequency = <100000>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_i2c2>; 178 status = "okay"; 179 180 ov2680: camera@36 { 181 compatible = "ovti,ov2680"; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_ov2680>; 184 reg = <0x36>; 185 clocks = <&osc>; 186 clock-names = "xvclk"; 187 reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; 188 DOVDD-supply = <&sw2_reg>; 189 DVDD-supply = <&sw2_reg>; 190 AVDD-supply = <®_peri_3p15v>; 191 192 port { 193 ov2680_to_mipi: endpoint { 194 remote-endpoint = <&mipi_from_sensor>; 195 clock-lanes = <0>; 196 data-lanes = <1>; 197 link-frequencies = /bits/ 64 <330000000>; 198 }; 199 }; 200 }; 201}; 202 203&i2c3 { 204 clock-frequency = <100000>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_i2c3>; 207 status = "okay"; 208}; 209 210&i2c4 { 211 clock-frequency = <100000>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_i2c4>; 214 status = "okay"; 215 216 codec: sgtl5000@a { 217 #sound-dai-cells = <0>; 218 reg = <0x0a>; 219 compatible = "fsl,sgtl5000"; 220 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_sai1_mclk>; 223 VDDA-supply = <&vgen4_reg>; 224 VDDIO-supply = <&vgen4_reg>; 225 VDDD-supply = <&vgen2_reg>; 226 }; 227 228 mpl3115@60 { 229 compatible = "fsl,mpl3115"; 230 reg = <0x60>; 231 }; 232}; 233 234&mipi_csi { 235 clock-frequency = <166000000>; 236 status = "okay"; 237 238 ports { 239 port@0 { 240 reg = <0>; 241 242 mipi_from_sensor: endpoint { 243 remote-endpoint = <&ov2680_to_mipi>; 244 data-lanes = <1>; 245 }; 246 }; 247 }; 248}; 249 250&sai1 { 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_sai1>; 253 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, 254 <&clks IMX7D_SAI1_ROOT_CLK>; 255 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 256 assigned-clock-rates = <0>, <36864000>; 257 status = "okay"; 258}; 259 260&uart1 { 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_uart1>; 263 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; 264 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 265 status = "okay"; 266}; 267 268&uart3 { 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_uart3>; 271 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; 272 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 273 uart-has-rtscts; 274 status = "okay"; 275 276 bluetooth { 277 compatible = "brcm,bcm4345c5"; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_bt_reg>; 280 shutdown-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; 281 max-speed = <3000000>; 282 }; 283}; 284 285&uart6 { 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_uart6>; 288 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 289 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 290 fsl,dte-mode; 291 status = "okay"; 292}; 293 294&usbotg1 { 295 dr_mode = "peripheral"; 296 status = "okay"; 297}; 298 299&usdhc1 { 300 #address-cells = <1>; 301 #size-cells = <0>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_usdhc1>; 304 bus-width = <4>; 305 keep-power-in-suspend; 306 no-1-8-v; 307 non-removable; 308 mmc-pwrseq = <&sdio_pwrseq>; 309 status = "okay"; 310 311 wifi@0 { 312 compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; 313 reg = <0>; 314 }; 315}; 316 317&usdhc3 { 318 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 319 pinctrl-0 = <&pinctrl_usdhc3>; 320 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 321 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 322 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; 323 assigned-clock-rates = <400000000>; 324 bus-width = <8>; 325 no-1-8-v; 326 fsl,tuning-step = <2>; 327 non-removable; 328 status = "okay"; 329}; 330 331&video_mux { 332 status = "okay"; 333}; 334 335&wdog1 { 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_wdog>; 338 fsl,ext-reset-output; 339 status = "okay"; 340}; 341 342&iomuxc { 343 pinctrl_brcm_reg: brcmreggrp { 344 fsl,pins = < 345 MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */ 346 >; 347 }; 348 349 pinctrl_bt_reg: btreggrp { 350 fsl,pins = < 351 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */ 352 >; 353 }; 354 355 pinctrl_gpio: gpiogrp { 356 fsl,pins = < 357 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14 358 >; 359 }; 360 361 pinctrl_i2c1: i2c1grp { 362 fsl,pins = < 363 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 364 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 365 >; 366 }; 367 368 pinctrl_i2c2: i2c2grp { 369 fsl,pins = < 370 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 371 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 372 >; 373 }; 374 375 pinctrl_i2c3: i2c3grp { 376 fsl,pins = < 377 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f 378 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f 379 >; 380 }; 381 382 pinctrl_i2c4: i2c4grp { 383 fsl,pins = < 384 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f 385 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f 386 >; 387 }; 388 389 pinctrl_ov2680: ov2660grp { 390 fsl,pins = < 391 MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14 392 >; 393 }; 394 395 pinctrl_sai1: sai1grp { 396 fsl,pins = < 397 MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f 398 MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f 399 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f 400 MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 401 >; 402 }; 403 404 pinctrl_sai1_mclk: sai1mclkgrp { 405 fsl,pins = < 406 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f 407 >; 408 }; 409 410 pinctrl_uart1: uart1grp { 411 fsl,pins = < 412 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 413 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 414 >; 415 }; 416 417 pinctrl_uart3: uart3grp { 418 fsl,pins = < 419 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 420 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 421 MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 422 MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 423 >; 424 }; 425 426 pinctrl_uart6: uart6grp { 427 fsl,pins = < 428 MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79 429 MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79 430 >; 431 }; 432 433 pinctrl_usdhc1: usdhc1grp { 434 fsl,pins = < 435 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 436 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 437 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 438 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 439 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 440 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 441 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */ 442 >; 443 }; 444 445 pinctrl_usdhc3: usdhc3grp { 446 fsl,pins = < 447 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 448 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 449 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 450 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 451 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 452 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 453 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 454 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 455 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 456 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 457 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19 458 >; 459 }; 460 461 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 462 fsl,pins = < 463 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a 464 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a 465 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a 466 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a 467 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a 468 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a 469 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a 470 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a 471 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a 472 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a 473 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a 474 >; 475 }; 476 477 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 478 fsl,pins = < 479 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b 480 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b 481 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b 482 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b 483 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b 484 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b 485 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b 486 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b 487 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b 488 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b 489 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b 490 >; 491 }; 492}; 493 494&iomuxc_lpsr { 495 pinctrl_wdog: wdoggrp { 496 fsl,pins = < 497 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 498 >; 499 }; 500}; 501