xref: /linux/scripts/dtc/include-prefixes/arm/nxp/imx/imx6ul-tx6ul-mainboard.dts (revision 115e74a29b530d121891238e9551c4bcdf7b04b5) 
1// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
2/*
3 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 */
5
6/dts-v1/;
7#include "imx6ul.dtsi"
8#include "imx6ul-tx6ul.dtsi"
9
10/ {
11	model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard";
12	compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
13
14	aliases {
15		lcdif-24bit-pins-a = &pinctrl_disp0_3;
16		mmc0 = &usdhc1;
17		/delete-property/ mmc1;
18		serial2 = &uart3;
19		serial4 = &uart5;
20	};
21	/delete-node/ sound;
22};
23
24&can1 {
25	xceiver-supply = <&reg_3v3>;
26};
27
28&can2 {
29	xceiver-supply = <&reg_3v3>;
30};
31
32&ds1339 {
33	status = "disabled";
34};
35
36&fec1 {
37	pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>;
38	/delete-node/ mdio;
39};
40
41&fec2 {
42	pinctrl-names = "default";
43	pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>;
44	phy-mode = "rmii";
45	phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
46	phy-supply = <&reg_3v3_etn>;
47	phy-handle = <&etnphy1>;
48	status = "okay";
49
50	mdio {
51		#address-cells = <1>;
52		#size-cells = <0>;
53
54		etnphy0: ethernet-phy@0 {
55			compatible = "ethernet-phy-ieee802.3-c22";
56			reg = <0>;
57			pinctrl-names = "default";
58			pinctrl-0 = <&pinctrl_etnphy0_int>;
59			interrupt-parent = <&gpio5>;
60			interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
61			interrupts-extended = <&gpio5 5 IRQ_TYPE_EDGE_FALLING>;
62			status = "okay";
63		};
64
65		etnphy1: ethernet-phy@2 {
66			compatible = "ethernet-phy-ieee802.3-c22";
67			reg = <2>;
68			pinctrl-names = "default";
69			pinctrl-0 = <&pinctrl_etnphy1_int>;
70			interrupt-parent = <&gpio4>;
71			interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
72			interrupts-extended = <&gpio4 27 IRQ_TYPE_EDGE_FALLING>;
73			status = "okay";
74		};
75	};
76};
77
78&i2c_gpio {
79	status = "disabled";
80};
81
82&i2c2 {
83	/delete-node/ codec@a;
84	/delete-node/ touchscreen@48;
85
86	rtc: rtc@6f {
87		compatible = "microchip,mcp7940x";
88		reg = <0x6f>;
89	};
90};
91
92&kpp {
93	status = "disabled";
94};
95
96&lcdif {
97	pinctrl-0 = <&pinctrl_disp0_3>;
98};
99
100&reg_usbotg_vbus {
101	status = "disabled";
102};
103
104&usdhc1 {
105	pinctrl-0 = <&pinctrl_usdhc1>;
106	non-removable;
107	/delete-property/ cd-gpios;
108	cap-sdio-irq;
109};
110
111&uart1 {
112	pinctrl-0 = <&pinctrl_uart1>;
113	/delete-property/ uart-has-rtscts;
114};
115
116&uart2 {
117	pinctrl-0 = <&pinctrl_uart2>;
118	/delete-property/ uart-has-rtscts;
119	status = "okay";
120};
121
122&uart3 {
123	pinctrl-names = "default";
124	pinctrl-0 = <&pinctrl_uart3>;
125	status = "okay";
126};
127
128&uart4 {
129	pinctrl-names = "default";
130	pinctrl-0 = <&pinctrl_uart4>;
131	status = "okay";
132};
133
134&uart5 {
135	pinctrl-names = "default";
136	pinctrl-0 = <&pinctrl_uart5>;
137	status = "okay";
138};
139
140&uart6 {
141	pinctrl-names = "default";
142	pinctrl-0 = <&pinctrl_uart6>;
143	status = "okay";
144};
145
146&uart7 {
147	pinctrl-names = "default";
148	pinctrl-0 = <&pinctrl_uart7>;
149	status = "okay";
150};
151
152&uart8 {
153	pinctrl-names = "default";
154	pinctrl-0 = <&pinctrl_uart8>;
155	status = "disabled"; /* conflicts with LCDIF */
156};
157
158&iomuxc {
159	hoggrp {
160		fsl,pins = <
161			MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x0b0b0 /* WLAN_RESET */
162		>;
163	};
164
165	pinctrl_disp0_3: disp0-3-grp {
166		fsl,pins = <
167			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x10 /* LSCLK */
168			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x10 /* OE_ACD */
169			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x10 /* HSYNC */
170			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x10 /* VSYNC */
171			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x10
172			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x10
173			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x10
174			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x10
175			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x10
176			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x10
177			/* LCD_DATA08..09 not wired */
178			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x10
179			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x10
180			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x10
181			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x10
182			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x10
183			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x10
184			/* LCD_DATA16..17 not wired */
185			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18	0x10
186			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19	0x10
187			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20	0x10
188			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21	0x10
189			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22	0x10
190			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23	0x10
191		>;
192	};
193
194	pinctrl_enet2_mdio: enet2-mdiogrp {
195		fsl,pins = <
196			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x0b0b0
197			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
198		>;
199	};
200
201	pinctrl_uart3: uart3grp {
202		fsl,pins = <
203			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x0b0b0
204			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x0b0b0
205		>;
206	};
207
208	pinctrl_uart4: uart4grp {
209		fsl,pins = <
210			MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX	0x0b0b0
211			MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX	0x0b0b0
212		>;
213	};
214
215	pinctrl_uart6: uart6grp {
216		fsl,pins = <
217			MX6UL_PAD_CSI_MCLK__UART6_DCE_TX	0x0b0b0
218			MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX	0x0b0b0
219		>;
220	};
221
222	pinctrl_uart7: uart7grp {
223		fsl,pins = <
224			MX6UL_PAD_LCD_DATA16__UART7_DCE_TX	0x0b0b0
225			MX6UL_PAD_LCD_DATA17__UART7_DCE_RX	0x0b0b0
226		>;
227	};
228
229	pinctrl_uart8: uart8grp {
230		fsl,pins = <
231			MX6UL_PAD_LCD_DATA20__UART8_DCE_TX	0x0b0b0
232			MX6UL_PAD_LCD_DATA21__UART8_DCE_RX	0x0b0b0
233		>;
234	};
235};
236