1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2017 exceet electronics GmbH 4 * Copyright (C) 2018 Kontron Electronics GmbH 5 * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 chosen { 12 stdout-path = &uart4; 13 }; 14 15 memory@80000000 { 16 reg = <0x80000000 0x10000000>; 17 device_type = "memory"; 18 }; 19}; 20 21&ecspi2 { 22 cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 23 pinctrl-names = "default"; 24 pinctrl-0 = <&pinctrl_ecspi2>; 25 status = "okay"; 26 27 flash@0 { 28 compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; 29 reg = <0>; 30 spi-max-frequency = <50000000>; 31 32 partitions { 33 compatible = "fixed-partitions"; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 partition@0 { 38 reg = <0x0 0xf0000>; 39 label = "u-boot"; 40 }; 41 42 partition@f0000 { 43 reg = <0xf0000 0x8000>; 44 label = "env"; 45 }; 46 47 partition@f8000 { 48 reg = <0xf8000 0x8000>; 49 label = "env_redundant"; 50 }; 51 }; 52 }; 53}; 54 55&fec1 { 56 pinctrl-names = "default"; 57 pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; 58 phy-mode = "rmii"; 59 phy-handle = <ðphy1>; 60 status = "okay"; 61 62 mdio { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 66 ethphy1: ethernet-phy@1 { 67 reg = <1>; 68 micrel,led-mode = <0>; 69 clocks = <&clks IMX6UL_CLK_ENET_REF>; 70 clock-names = "rmii-ref"; 71 }; 72 }; 73}; 74 75&fec2 { 76 phy-mode = "rmii"; 77 status = "disabled"; 78}; 79 80&qspi { 81 pinctrl-names = "default"; 82 pinctrl-0 = <&pinctrl_qspi>; 83 status = "okay"; 84 85 flash@0 { 86 #address-cells = <1>; 87 #size-cells = <1>; 88 compatible = "spi-nand"; 89 spi-max-frequency = <104000000>; 90 spi-tx-bus-width = <4>; 91 spi-rx-bus-width = <4>; 92 reg = <0>; 93 }; 94}; 95 96&wdog1 { 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_wdog>; 99 fsl,ext-reset-output; 100 status = "okay"; 101}; 102 103&iomuxc { 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_reset_out>; 106 107 pinctrl_ecspi2: ecspi2grp { 108 fsl,pins = < 109 MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 110 MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 111 MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 112 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 113 >; 114 }; 115 116 pinctrl_enet1: enet1grp { 117 fsl,pins = < 118 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 119 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 120 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 121 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 122 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 123 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 124 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 125 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 126 >; 127 }; 128 129 pinctrl_enet1_mdio: enet1mdiogrp { 130 fsl,pins = < 131 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 132 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 133 >; 134 }; 135 136 pinctrl_qspi: qspigrp { 137 fsl,pins = < 138 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 139 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 140 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 141 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 142 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 143 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 144 >; 145 }; 146 147 pinctrl_reset_out: rstoutgrp { 148 fsl,pins = < 149 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 150 >; 151 }; 152 153 pinctrl_wdog: wdoggrp { 154 fsl,pins = < 155 MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0 156 >; 157 }; 158}; 159