1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2017 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 chosen { 12 stdout-path = &uart2; 13 }; 14 15 backlight { 16 compatible = "pwm-backlight"; 17 pwms = <&pwm1 0 5000000 0>; 18 brightness-levels = < 19 0 1 2 3 4 5 6 7 8 9 20 10 11 12 13 14 15 16 17 18 19 21 20 21 22 23 24 25 26 27 28 29 22 30 31 32 33 34 35 36 37 38 39 23 40 41 42 43 44 45 46 47 48 49 24 50 51 52 53 54 55 56 57 58 59 25 60 61 62 63 64 65 66 67 68 69 26 70 71 72 73 74 75 76 77 78 79 27 80 81 82 83 84 85 86 87 88 89 28 90 91 92 93 94 95 96 97 98 99 29 100 30 >; 31 default-brightness-level = <100>; 32 }; 33 34 gpio-keys { 35 compatible = "gpio-keys"; 36 37 user-pb { 38 label = "user_pb"; 39 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 40 linux,code = <BTN_0>; 41 }; 42 43 user-pb1x { 44 label = "user_pb1x"; 45 linux,code = <BTN_1>; 46 interrupt-parent = <&gsc>; 47 interrupts = <0>; 48 }; 49 50 key-erased { 51 label = "key-erased"; 52 linux,code = <BTN_2>; 53 interrupt-parent = <&gsc>; 54 interrupts = <1>; 55 }; 56 57 eeprom-wp { 58 label = "eeprom_wp"; 59 linux,code = <BTN_3>; 60 interrupt-parent = <&gsc>; 61 interrupts = <2>; 62 }; 63 64 tamper { 65 label = "tamper"; 66 linux,code = <BTN_4>; 67 interrupt-parent = <&gsc>; 68 interrupts = <5>; 69 }; 70 71 switch-hold { 72 label = "switch_hold"; 73 linux,code = <BTN_5>; 74 interrupt-parent = <&gsc>; 75 interrupts = <7>; 76 }; 77 }; 78 79 leds { 80 compatible = "gpio-leds"; 81 pinctrl-names = "default"; 82 pinctrl-0 = <&pinctrl_gpio_leds>; 83 84 led0: led-user1 { 85 label = "user1"; 86 gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 87 default-state = "off"; 88 }; 89 }; 90 91 memory@10000000 { 92 device_type = "memory"; 93 reg = <0x10000000 0x40000000>; 94 }; 95 96 reg_5p0v: regulator-5p0v { 97 compatible = "regulator-fixed"; 98 regulator-name = "5P0V"; 99 regulator-min-microvolt = <5000000>; 100 regulator-max-microvolt = <5000000>; 101 regulator-always-on; 102 }; 103 104 reg_3p3v: regulator-3p3v { 105 compatible = "regulator-fixed"; 106 regulator-name = "3P3V"; 107 regulator-min-microvolt = <3300000>; 108 regulator-max-microvolt = <3300000>; 109 regulator-always-on; 110 }; 111 112 reg_2p5v: regulator-2p5v { 113 compatible = "regulator-fixed"; 114 regulator-name = "2P5V"; 115 regulator-min-microvolt = <2500000>; 116 regulator-max-microvolt = <2500000>; 117 regulator-always-on; 118 }; 119 120 reg_usb_h1_vbus: regulator-usb-h1-vbus { 121 compatible = "regulator-fixed"; 122 regulator-name = "usb_h1_vbus"; 123 regulator-min-microvolt = <5000000>; 124 regulator-max-microvolt = <5000000>; 125 gpio = <&gpio3 30 0>; 126 enable-active-high; 127 }; 128 129 reg_usb_otg_vbus: regulator-usb-otg-vbus { 130 compatible = "regulator-fixed"; 131 regulator-name = "usb_otg_vbus"; 132 regulator-min-microvolt = <5000000>; 133 regulator-max-microvolt = <5000000>; 134 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; 135 enable-active-high; 136 }; 137 138 reg_12p0: regulator-12p0v { 139 compatible = "regulator-fixed"; 140 regulator-name = "12P0V"; 141 regulator-min-microvolt = <12000000>; 142 regulator-max-microvolt = <12000000>; 143 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 144 enable-active-high; 145 }; 146 147 sound { 148 compatible = "fsl,imx-audio-tlv320"; 149 model = "imx-tlv320"; 150 ssi-controller = <&ssi1>; 151 audio-codec = <&tlv320aic3105>; 152 /* routing of sink, source */ 153 audio-routing = 154 /* TLV320 LINE1L pin <-> Mic Jack connector */ 155 "LINE1L", "Mic Jack", 156 /* board Headphone Jack <-> HPOUT */ 157 "Headphone Jack", "HPLOUT", 158 "Headphone Jack", "HPROUT", 159 "Mic Jack", "Mic Bias"; 160 mux-int-port = <1>; 161 mux-ext-port = <6>; 162 }; 163}; 164 165&audmux { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_audmux>; 168 status = "okay"; 169}; 170 171&clks { 172 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 173 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 174 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 175 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 176}; 177 178&fec { 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_enet>; 181 phy-mode = "rgmii-id"; 182 status = "okay"; 183}; 184 185&i2c1 { 186 clock-frequency = <100000>; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_i2c1>; 189 status = "okay"; 190 191 gsc: gsc@20 { 192 compatible = "gw,gsc"; 193 reg = <0x20>; 194 interrupt-parent = <&gpio1>; 195 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 196 interrupt-controller; 197 #interrupt-cells = <1>; 198 #size-cells = <0>; 199 200 adc { 201 compatible = "gw,gsc-adc"; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 205 channel@0 { 206 gw,mode = <0>; 207 reg = <0x00>; 208 label = "temp"; 209 }; 210 211 channel@2 { 212 gw,mode = <1>; 213 reg = <0x02>; 214 label = "vdd_vin"; 215 }; 216 217 channel@5 { 218 gw,mode = <1>; 219 reg = <0x05>; 220 label = "vdd_3p3"; 221 }; 222 223 channel@8 { 224 gw,mode = <1>; 225 reg = <0x08>; 226 label = "vdd_bat"; 227 }; 228 229 channel@b { 230 gw,mode = <1>; 231 reg = <0x0b>; 232 label = "vdd_5p0"; 233 }; 234 235 channel@e { 236 gw,mode = <1>; 237 reg = <0xe>; 238 label = "vdd_arm"; 239 }; 240 241 channel@11 { 242 gw,mode = <1>; 243 reg = <0x11>; 244 label = "vdd_soc"; 245 }; 246 247 channel@14 { 248 gw,mode = <1>; 249 reg = <0x14>; 250 label = "vdd_3p0"; 251 }; 252 253 channel@17 { 254 gw,mode = <1>; 255 reg = <0x17>; 256 label = "vdd_1p5"; 257 }; 258 259 channel@1d { 260 gw,mode = <1>; 261 reg = <0x1d>; 262 label = "vdd_1p8"; 263 }; 264 265 channel@20 { 266 gw,mode = <1>; 267 reg = <0x20>; 268 label = "vdd_an1"; 269 }; 270 271 channel@23 { 272 gw,mode = <1>; 273 reg = <0x23>; 274 label = "vdd_2p5"; 275 }; 276 }; 277 }; 278 279 gsc_gpio: gpio@23 { 280 compatible = "nxp,pca9555"; 281 reg = <0x23>; 282 gpio-controller; 283 #gpio-cells = <2>; 284 interrupt-parent = <&gsc>; 285 interrupts = <4>; 286 }; 287 288 eeprom1: eeprom@50 { 289 compatible = "atmel,24c02"; 290 reg = <0x50>; 291 pagesize = <16>; 292 }; 293 294 eeprom2: eeprom@51 { 295 compatible = "atmel,24c02"; 296 reg = <0x51>; 297 pagesize = <16>; 298 }; 299 300 eeprom3: eeprom@52 { 301 compatible = "atmel,24c02"; 302 reg = <0x52>; 303 pagesize = <16>; 304 }; 305 306 eeprom4: eeprom@53 { 307 compatible = "atmel,24c02"; 308 reg = <0x53>; 309 pagesize = <16>; 310 }; 311 312 dts1672: rtc@68 { 313 compatible = "dallas,ds1672"; 314 reg = <0x68>; 315 }; 316}; 317 318&i2c2 { 319 clock-frequency = <400000>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_i2c2>; 322 status = "okay"; 323 324 ltc3676: pmic@3c { 325 compatible = "lltc,ltc3676"; 326 reg = <0x3c>; 327 interrupt-parent = <&gpio1>; 328 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 329 330 regulators { 331 /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */ 332 reg_1p8v: sw1 { 333 regulator-name = "vdd1p8"; 334 regulator-min-microvolt = <1033310>; 335 regulator-max-microvolt = <2004000>; 336 lltc,fb-voltage-divider = <301000 200000>; 337 regulator-ramp-delay = <7000>; 338 regulator-boot-on; 339 regulator-always-on; 340 }; 341 342 /* VDD_DDR (1+R1/R2 = 2.105) */ 343 reg_vdd_ddr: sw2 { 344 regulator-name = "vddddr"; 345 regulator-min-microvolt = <868310>; 346 regulator-max-microvolt = <1684000>; 347 lltc,fb-voltage-divider = <221000 200000>; 348 regulator-ramp-delay = <7000>; 349 regulator-boot-on; 350 regulator-always-on; 351 }; 352 353 /* VDD_ARM (1+R1/R2 = 1.635) */ 354 reg_vdd_arm: sw3 { 355 regulator-name = "vddarm"; 356 regulator-min-microvolt = <674400>; 357 regulator-max-microvolt = <1308000>; 358 lltc,fb-voltage-divider = <127000 200000>; 359 regulator-ramp-delay = <7000>; 360 regulator-boot-on; 361 regulator-always-on; 362 linux,phandle = <®_vdd_arm>; 363 }; 364 365 /* VDD_SOC (1+R1/R2 = 1.635) */ 366 reg_vdd_soc: sw4 { 367 regulator-name = "vddsoc"; 368 regulator-min-microvolt = <674400>; 369 regulator-max-microvolt = <1308000>; 370 lltc,fb-voltage-divider = <127000 200000>; 371 regulator-ramp-delay = <7000>; 372 regulator-boot-on; 373 regulator-always-on; 374 linux,phandle = <®_vdd_soc>; 375 }; 376 377 /* VDD_1P0 (1+R1/R2 = 1.38): */ 378 reg_1p0v: ldo2 { 379 regulator-name = "vdd1p0"; 380 regulator-min-microvolt = <1002777>; 381 regulator-max-microvolt = <1002777>; 382 lltc,fb-voltage-divider = <100000 261000>; 383 regulator-boot-on; 384 regulator-always-on; 385 }; 386 387 /* VDD_HIGH (1+R1/R2 = 4.17) */ 388 reg_3p0v: ldo4 { 389 regulator-name = "vdd3p0"; 390 regulator-min-microvolt = <3023250>; 391 regulator-max-microvolt = <3023250>; 392 lltc,fb-voltage-divider = <634000 200000>; 393 regulator-boot-on; 394 regulator-always-on; 395 }; 396 }; 397 }; 398}; 399 400&i2c3 { 401 clock-frequency = <400000>; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pinctrl_i2c3>; 404 status = "okay"; 405 406 tlv320aic3105: codec@18 { 407 compatible = "ti,tlv320aic3x"; 408 reg = <0x18>; 409 reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; 410 clocks = <&clks IMX6QDL_CLK_CKO>; 411 ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ 412 /* Regulators */ 413 DRVDD-supply = <®_3p3v>; 414 AVDD-supply = <®_3p3v>; 415 IOVDD-supply = <®_3p3v>; 416 DVDD-supply = <®_1p8v>; 417 }; 418 419 accelerometer@1d { 420 compatible = "fsl,mma8451"; 421 reg = <0x1d>; 422 interrupt-parent = <&gpio7>; 423 interrupts = <11 IRQ_TYPE_EDGE_RISING>; 424 interrupt-names = "INT2"; 425 }; 426 427 /* headphone detect */ 428 ts3a227e@3b { 429 compatible = "ti,ts3a227e"; 430 reg = <0x3b>; 431 interrupt-parent = <&gpio5>; 432 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 433 ti,micbias = <4>; /* 2.5V micbias */ 434 }; 435}; 436 437&ldb { 438 status = "okay"; 439 440 lvds-channel@0 { 441 fsl,data-mapping = "spwg"; 442 fsl,data-width = <18>; 443 status = "okay"; 444 445 display-timings { 446 native-mode = <&timing0>; 447 timing0: timing-g101evn010 { 448 clock-frequency = <68930000>; 449 hactive = <1280>; 450 vactive = <800>; 451 hback-porch = <220>; 452 hfront-porch = <40>; 453 vback-porch = <21>; 454 vfront-porch = <7>; 455 hsync-len = <60>; 456 vsync-len = <10>; 457 }; 458 }; 459 }; 460}; 461 462&pwm1 { 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pinctrl_pwm1>; 465 status = "okay"; 466}; 467 468&ssi1 { 469 status = "okay"; 470}; 471 472&uart1 { 473 pinctrl-names = "default"; 474 pinctrl-0 = <&pinctrl_uart1>; 475 status = "okay"; 476}; 477 478&uart2 { 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pinctrl_uart2>; 481 status = "okay"; 482}; 483 484&usbotg { 485 vbus-supply = <®_usb_otg_vbus>; 486 pinctrl-names = "default"; 487 pinctrl-0 = <&pinctrl_usbotg>; 488 disable-over-current; 489 status = "okay"; 490}; 491 492&usbh1 { 493 vbus-supply = <®_usb_h1_vbus>; 494 status = "okay"; 495}; 496 497&usdhc1 { 498 pinctrl-names = "default"; 499 pinctrl-0 = <&pinctrl_usdhc1_200mhz>; 500 vmmc-supply = <®_3p3v>; 501 non-removable; 502 bus-width = <4>; 503 status = "okay"; 504}; 505 506&usdhc2 { 507 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 508 pinctrl-0 = <&pinctrl_usdhc2>; 509 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 510 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 511 cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 512 vmmc-supply = <®_3p3v>; 513 max-frequency = <100000000>; 514 status = "okay"; 515}; 516 517&usdhc3 { 518 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 519 pinctrl-0 = <&pinctrl_usdhc3>; 520 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 521 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 522 non-removable; 523 vmmc-supply = <®_3p3v>; 524 keep-power-in-suspend; 525 status = "okay"; 526}; 527 528&wdog1 { 529 pinctrl-names = "default"; 530 pinctrl-0 = <&pinctrl_wdog>; 531 fsl,ext-reset-output; 532}; 533 534&iomuxc { 535 pinctrl_audmux: audmuxgrp { 536 fsl,pins = < 537 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 538 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 539 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 540 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 541 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */ 542 >; 543 }; 544 545 pinctrl_enet: enetgrp { 546 fsl,pins = < 547 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 548 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 549 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 550 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 551 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 552 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 553 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 554 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 555 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 556 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 557 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 558 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 559 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 560 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 561 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 562 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 563 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */ 564 >; 565 }; 566 567 pinctrl_gpio_leds: gpioledsgrp { 568 fsl,pins = < 569 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 570 >; 571 }; 572 573 pinctrl_i2c1: i2c1grp { 574 fsl,pins = < 575 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 576 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 577 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 578 >; 579 }; 580 581 pinctrl_i2c2: i2c2grp { 582 fsl,pins = < 583 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 584 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 585 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 586 >; 587 }; 588 589 pinctrl_i2c3: i2c3grp { 590 fsl,pins = < 591 /* I2C3 */ 592 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 593 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 594 595 /* Headphone Detect */ 596 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */ 597 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */ 598 599 /* Codec */ 600 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */ 601 602 /* Touch Controller */ 603 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */ 604 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */ 605 606 /* Stow Sensor */ 607 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */ 608 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */ 609 >; 610 }; 611 612 pinctrl_pwm1: pwm1grp { 613 fsl,pins = < 614 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 615 >; 616 }; 617 618 pinctrl_uart1: uart1grp { 619 fsl,pins = < 620 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 621 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 622 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */ 623 >; 624 }; 625 626 pinctrl_uart2: uart2grp { 627 fsl,pins = < 628 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 629 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 630 >; 631 }; 632 633 pinctrl_usbotg: usbotggrp { 634 fsl,pins = < 635 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 636 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */ 637 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 638 >; 639 }; 640 641 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 642 fsl,pins = < 643 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */ 644 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */ 645 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */ 646 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */ 647 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */ 648 649 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 650 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9 651 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 652 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 653 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 654 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 655 >; 656 }; 657 658 pinctrl_usdhc2: usdhc2grp { 659 fsl,pins = < 660 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 661 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 662 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 663 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 664 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 665 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 666 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */ 667 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059 668 >; 669 }; 670 671 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { 672 fsl,pins = < 673 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 674 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 675 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 676 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 677 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 678 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 679 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */ 680 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9 681 >; 682 }; 683 684 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { 685 fsl,pins = < 686 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 687 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 688 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 689 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 690 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 691 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 692 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */ 693 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9 694 >; 695 }; 696 697 pinctrl_usdhc3: usdhc3grp { 698 fsl,pins = < 699 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 700 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 701 MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 702 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 703 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 704 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 705 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 706 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 707 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 708 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 709 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 710 >; 711 }; 712 713 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 714 fsl,pins = < 715 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 716 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 717 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 718 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 719 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 720 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 721 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 722 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 723 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 724 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 725 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 726 >; 727 }; 728 729 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 730 fsl,pins = < 731 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 732 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 733 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 734 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 735 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 736 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 737 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 738 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 739 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 740 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 741 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 742 >; 743 }; 744 745 pinctrl_wdog: wdoggrp { 746 fsl,pins = < 747 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 748 >; 749 }; 750}; 751