1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2016 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 led0 = &led0; 14 led1 = &led1; 15 nand = &gpmi; 16 usb0 = &usbh1; 17 usb1 = &usbotg; 18 }; 19 20 chosen { 21 stdout-path = &uart2; 22 }; 23 24 gpio-keys { 25 compatible = "gpio-keys"; 26 27 user-pb { 28 label = "user_pb"; 29 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 30 linux,code = <BTN_0>; 31 }; 32 33 user-pb1x { 34 label = "user_pb1x"; 35 linux,code = <BTN_1>; 36 interrupt-parent = <&gsc>; 37 interrupts = <0>; 38 }; 39 40 key-erased { 41 label = "key-erased"; 42 linux,code = <BTN_2>; 43 interrupt-parent = <&gsc>; 44 interrupts = <1>; 45 }; 46 47 eeprom-wp { 48 label = "eeprom_wp"; 49 linux,code = <BTN_3>; 50 interrupt-parent = <&gsc>; 51 interrupts = <2>; 52 }; 53 54 tamper { 55 label = "tamper"; 56 linux,code = <BTN_4>; 57 interrupt-parent = <&gsc>; 58 interrupts = <5>; 59 }; 60 61 switch-hold { 62 label = "switch_hold"; 63 linux,code = <BTN_5>; 64 interrupt-parent = <&gsc>; 65 interrupts = <7>; 66 }; 67 }; 68 69 leds { 70 compatible = "gpio-leds"; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_gpio_leds>; 73 74 led0: led-user1 { 75 label = "user1"; 76 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 77 default-state = "on"; 78 linux,default-trigger = "heartbeat"; 79 }; 80 81 led1: led-user2 { 82 label = "user2"; 83 gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 84 default-state = "off"; 85 }; 86 }; 87 88 memory@10000000 { 89 device_type = "memory"; 90 reg = <0x10000000 0x20000000>; 91 }; 92 93 pps { 94 compatible = "pps-gpio"; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_pps>; 97 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 98 status = "okay"; 99 }; 100 101 reg_5p0v: regulator-5p0v { 102 compatible = "regulator-fixed"; 103 regulator-name = "5P0V"; 104 regulator-min-microvolt = <5000000>; 105 regulator-max-microvolt = <5000000>; 106 regulator-always-on; 107 }; 108 109 reg_usb_otg_vbus: regulator-usb-otg-vbus { 110 compatible = "regulator-fixed"; 111 regulator-name = "usb_otg_vbus"; 112 regulator-min-microvolt = <5000000>; 113 regulator-max-microvolt = <5000000>; 114 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 115 enable-active-high; 116 }; 117}; 118 119&gpmi { 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_gpmi_nand>; 122 status = "okay"; 123}; 124 125&hdmi { 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_hdmi>; 128 ddc-i2c-bus = <&i2c3>; 129 status = "okay"; 130}; 131 132&i2c1 { 133 clock-frequency = <100000>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_i2c1>; 136 status = "okay"; 137 138 gsc: gsc@20 { 139 compatible = "gw,gsc"; 140 reg = <0x20>; 141 interrupt-parent = <&gpio1>; 142 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 143 interrupt-controller; 144 #interrupt-cells = <1>; 145 #size-cells = <0>; 146 147 adc { 148 compatible = "gw,gsc-adc"; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 152 channel@0 { 153 gw,mode = <0>; 154 reg = <0x00>; 155 label = "temp"; 156 }; 157 158 channel@2 { 159 gw,mode = <1>; 160 reg = <0x02>; 161 label = "vdd_vin"; 162 }; 163 164 channel@5 { 165 gw,mode = <1>; 166 reg = <0x05>; 167 label = "vdd_3p3"; 168 }; 169 170 channel@8 { 171 gw,mode = <1>; 172 reg = <0x08>; 173 label = "vdd_bat"; 174 }; 175 176 channel@b { 177 gw,mode = <1>; 178 reg = <0x0b>; 179 label = "vdd_5p0"; 180 }; 181 182 channel@e { 183 gw,mode = <1>; 184 reg = <0xe>; 185 label = "vdd_arm"; 186 }; 187 188 channel@11 { 189 gw,mode = <1>; 190 reg = <0x11>; 191 label = "vdd_soc"; 192 }; 193 194 channel@14 { 195 gw,mode = <1>; 196 reg = <0x14>; 197 label = "vdd_3p0"; 198 }; 199 200 channel@17 { 201 gw,mode = <1>; 202 reg = <0x17>; 203 label = "vdd_1p5"; 204 }; 205 206 channel@1d { 207 gw,mode = <1>; 208 reg = <0x1d>; 209 label = "vdd_1p8a"; 210 }; 211 212 channel@20 { 213 gw,mode = <1>; 214 reg = <0x20>; 215 label = "vdd_1p0b"; 216 }; 217 218 channel@26 { 219 gw,mode = <1>; 220 reg = <0x26>; 221 label = "vdd_an1"; 222 }; 223 }; 224 }; 225 226 gsc_gpio: gpio@23 { 227 compatible = "nxp,pca9555"; 228 reg = <0x23>; 229 gpio-controller; 230 #gpio-cells = <2>; 231 interrupt-parent = <&gsc>; 232 interrupts = <4>; 233 }; 234 235 eeprom1: eeprom@50 { 236 compatible = "atmel,24c02"; 237 reg = <0x50>; 238 pagesize = <16>; 239 }; 240 241 eeprom2: eeprom@51 { 242 compatible = "atmel,24c02"; 243 reg = <0x51>; 244 pagesize = <16>; 245 }; 246 247 eeprom3: eeprom@52 { 248 compatible = "atmel,24c02"; 249 reg = <0x52>; 250 pagesize = <16>; 251 }; 252 253 eeprom4: eeprom@53 { 254 compatible = "atmel,24c02"; 255 reg = <0x53>; 256 pagesize = <16>; 257 }; 258 259 rtc: ds1672@68 { 260 compatible = "dallas,ds1672"; 261 reg = <0x68>; 262 }; 263}; 264 265&i2c2 { 266 clock-frequency = <100000>; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_i2c2>; 269 status = "okay"; 270 271 magn@1c { 272 compatible = "st,lsm9ds1-magn"; 273 reg = <0x1c>; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&pinctrl_mag>; 276 interrupt-parent = <&gpio1>; 277 interrupts = <2 IRQ_TYPE_EDGE_RISING>; 278 }; 279 280 imu@6a { 281 compatible = "st,lsm9ds1-imu"; 282 reg = <0x6a>; 283 st,drdy-int-pin = <1>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_imu>; 286 interrupt-parent = <&gpio7>; 287 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; 288 }; 289 290 ltc3676: pmic@3c { 291 compatible = "lltc,ltc3676"; 292 reg = <0x3c>; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_pmic>; 295 interrupt-parent = <&gpio1>; 296 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 297 298 regulators { 299 /* VDD_SOC (1+R1/R2 = 1.635) */ 300 reg_vdd_soc: sw1 { 301 regulator-name = "vddsoc"; 302 regulator-min-microvolt = <674400>; 303 regulator-max-microvolt = <1308000>; 304 lltc,fb-voltage-divider = <127000 200000>; 305 regulator-ramp-delay = <7000>; 306 regulator-boot-on; 307 regulator-always-on; 308 }; 309 310 /* VDD_DDR (1+R1/R2 = 2.105) */ 311 reg_vdd_ddr: sw2 { 312 regulator-name = "vddddr"; 313 regulator-min-microvolt = <868310>; 314 regulator-max-microvolt = <1684000>; 315 lltc,fb-voltage-divider = <221000 200000>; 316 regulator-ramp-delay = <7000>; 317 regulator-boot-on; 318 regulator-always-on; 319 }; 320 321 /* VDD_ARM (1+R1/R2 = 1.635) */ 322 reg_vdd_arm: sw3 { 323 regulator-name = "vddarm"; 324 regulator-min-microvolt = <674400>; 325 regulator-max-microvolt = <1308000>; 326 lltc,fb-voltage-divider = <127000 200000>; 327 regulator-ramp-delay = <7000>; 328 regulator-boot-on; 329 regulator-always-on; 330 }; 331 332 /* VDD_3P3 (1+R1/R2 = 1.281) */ 333 reg_3p3v: sw4 { 334 regulator-name = "vdd3p3"; 335 regulator-min-microvolt = <1880000>; 336 regulator-max-microvolt = <3647000>; 337 lltc,fb-voltage-divider = <200000 56200>; 338 regulator-ramp-delay = <7000>; 339 regulator-boot-on; 340 regulator-always-on; 341 }; 342 343 /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */ 344 reg_1p8a: ldo2 { 345 regulator-name = "vdd1p8a"; 346 regulator-min-microvolt = <1816125>; 347 regulator-max-microvolt = <1816125>; 348 lltc,fb-voltage-divider = <301000 200000>; 349 regulator-boot-on; 350 regulator-always-on; 351 }; 352 353 /* VDD_1P8b: microSD VDD_1P8 */ 354 reg_1p8b: ldo3 { 355 regulator-name = "vdd1p8b"; 356 regulator-min-microvolt = <1800000>; 357 regulator-max-microvolt = <1800000>; 358 regulator-boot-on; 359 }; 360 361 /* VDD_HIGH (1+R1/R2 = 4.17) */ 362 reg_3p0v: ldo4 { 363 regulator-name = "vdd3p0"; 364 regulator-min-microvolt = <3023250>; 365 regulator-max-microvolt = <3023250>; 366 lltc,fb-voltage-divider = <634000 200000>; 367 regulator-boot-on; 368 regulator-always-on; 369 }; 370 }; 371 }; 372}; 373 374&i2c3 { 375 clock-frequency = <100000>; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pinctrl_i2c3>; 378 status = "okay"; 379 380 adv7180: camera@20 { 381 compatible = "adi,adv7180"; 382 pinctrl-names = "default"; 383 pinctrl-0 = <&pinctrl_adv7180>; 384 reg = <0x20>; 385 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; 386 interrupt-parent = <&gpio5>; 387 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 388 389 port { 390 adv7180_to_ipu1_csi0_mux: endpoint { 391 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 392 bus-width = <8>; 393 }; 394 }; 395 }; 396}; 397 398&ipu1_csi0_from_ipu1_csi0_mux { 399 bus-width = <8>; 400}; 401 402&ipu1_csi0_mux_from_parallel_sensor { 403 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; 404 bus-width = <8>; 405}; 406 407&ipu1_csi0 { 408 pinctrl-names = "default"; 409 pinctrl-0 = <&pinctrl_ipu1_csi0>; 410}; 411 412&pcie { 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pinctrl_pcie>; 415 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 416 status = "okay"; 417}; 418 419&pwm2 { 420 pinctrl-names = "default"; 421 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 422 status = "disabled"; 423}; 424 425&pwm3 { 426 pinctrl-names = "default"; 427 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 428 status = "disabled"; 429}; 430 431&pwm4 { 432 pinctrl-names = "default"; 433 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ 434 status = "disabled"; 435}; 436 437&uart2 { 438 pinctrl-names = "default"; 439 pinctrl-0 = <&pinctrl_uart2>; 440 status = "okay"; 441}; 442 443&uart3 { 444 pinctrl-names = "default"; 445 pinctrl-0 = <&pinctrl_uart3>; 446 status = "okay"; 447}; 448 449&uart4 { 450 pinctrl-names = "default"; 451 pinctrl-0 = <&pinctrl_uart4>; 452 status = "okay"; 453}; 454 455&uart5 { 456 pinctrl-names = "default"; 457 pinctrl-0 = <&pinctrl_uart5>; 458 status = "okay"; 459}; 460 461&usbh1 { 462 status = "okay"; 463}; 464 465&usbotg { 466 vbus-supply = <®_usb_otg_vbus>; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pinctrl_usbotg>; 469 disable-over-current; 470 status = "okay"; 471}; 472 473&usdhc3 { 474 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 475 pinctrl-0 = <&pinctrl_usdhc3>; 476 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 477 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 478 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 479 status = "okay"; 480}; 481 482&wdog1 { 483 pinctrl-names = "default"; 484 pinctrl-0 = <&pinctrl_wdog>; 485 fsl,ext-reset-output; 486}; 487 488&iomuxc { 489 pinctrl_adv7180: adv7180grp { 490 fsl,pins = < 491 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 492 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 493 >; 494 }; 495 496 pinctrl_gpmi_nand: gpminandgrp { 497 fsl,pins = < 498 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 499 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 500 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 501 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 502 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 503 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 504 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 505 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 506 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 507 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 508 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 509 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 510 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 511 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 512 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 513 >; 514 }; 515 516 pinctrl_hdmi: hdmigrp { 517 fsl,pins = < 518 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 519 >; 520 }; 521 522 pinctrl_i2c1: i2c1grp { 523 fsl,pins = < 524 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 525 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 526 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 527 >; 528 }; 529 530 pinctrl_i2c2: i2c2grp { 531 fsl,pins = < 532 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 533 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 534 >; 535 }; 536 537 pinctrl_i2c3: i2c3grp { 538 fsl,pins = < 539 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 540 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 541 >; 542 }; 543 544 pinctrl_imu: imugrp { 545 fsl,pins = < 546 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 547 >; 548 }; 549 550 pinctrl_ipu1_csi0: ipu1csi0grp { 551 fsl,pins = < 552 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 553 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 554 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 555 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 556 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 557 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 558 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 559 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 560 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 561 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 562 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 563 >; 564 }; 565 566 pinctrl_gpio_leds: gpioledsgrp { 567 fsl,pins = < 568 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 569 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 570 >; 571 }; 572 573 pinctrl_mag: maggrp { 574 fsl,pins = < 575 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 576 >; 577 }; 578 579 pinctrl_pcie: pciegrp { 580 fsl,pins = < 581 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 582 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ 583 >; 584 }; 585 586 pinctrl_pmic: pmicgrp { 587 fsl,pins = < 588 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 589 >; 590 }; 591 592 pinctrl_pps: ppsgrp { 593 fsl,pins = < 594 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 595 >; 596 }; 597 598 pinctrl_pwm2: pwm2grp { 599 fsl,pins = < 600 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 601 >; 602 }; 603 604 pinctrl_pwm3: pwm3grp { 605 fsl,pins = < 606 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 607 >; 608 }; 609 610 pinctrl_pwm4: pwm4grp { 611 fsl,pins = < 612 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 613 >; 614 }; 615 616 pinctrl_uart2: uart2grp { 617 fsl,pins = < 618 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 619 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 620 >; 621 }; 622 623 pinctrl_uart3: uart3grp { 624 fsl,pins = < 625 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 626 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 627 >; 628 }; 629 630 pinctrl_uart4: uart4grp { 631 fsl,pins = < 632 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 633 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 634 >; 635 }; 636 637 pinctrl_uart5: uart5grp { 638 fsl,pins = < 639 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 640 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 641 >; 642 }; 643 644 pinctrl_usbotg: usbotggrp { 645 fsl,pins = < 646 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 647 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 648 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 649 >; 650 }; 651 652 pinctrl_usdhc3: usdhc3grp { 653 fsl,pins = < 654 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 655 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 656 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 657 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 658 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 659 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 660 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 661 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 662 >; 663 }; 664 665 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 666 fsl,pins = < 667 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 668 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 669 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 670 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 671 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 672 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 673 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 674 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 675 >; 676 }; 677 678 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 679 fsl,pins = < 680 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 681 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 682 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 683 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 684 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 685 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 686 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 687 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 688 >; 689 }; 690 691 pinctrl_wdog: wdoggrp { 692 fsl,pins = < 693 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 694 >; 695 }; 696}; 697