1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright 2015 Endless Mobile, Inc. 4 * Author: Carlo Caione <carlo@endlessm.com> 5 */ 6 7#include <dt-bindings/clock/meson8-ddr-clkc.h> 8#include <dt-bindings/clock/meson8b-clkc.h> 9#include <dt-bindings/gpio/meson8b-gpio.h> 10#include <dt-bindings/power/meson8-power.h> 11#include <dt-bindings/reset/amlogic,meson8b-reset.h> 12#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 13#include <dt-bindings/thermal/thermal.h> 14#include "meson.dtsi" 15 16/ { 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@200 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a5"; 24 next-level-cache = <&L2>; 25 reg = <0x200>; 26 enable-method = "amlogic,meson8b-smp"; 27 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; 28 operating-points-v2 = <&cpu_opp_table>; 29 clocks = <&clkc CLKID_CPUCLK>; 30 #cooling-cells = <2>; /* min followed by max */ 31 }; 32 33 cpu1: cpu@201 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a5"; 36 next-level-cache = <&L2>; 37 reg = <0x201>; 38 enable-method = "amlogic,meson8b-smp"; 39 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; 40 operating-points-v2 = <&cpu_opp_table>; 41 clocks = <&clkc CLKID_CPUCLK>; 42 #cooling-cells = <2>; /* min followed by max */ 43 }; 44 45 cpu2: cpu@202 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a5"; 48 next-level-cache = <&L2>; 49 reg = <0x202>; 50 enable-method = "amlogic,meson8b-smp"; 51 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; 52 operating-points-v2 = <&cpu_opp_table>; 53 clocks = <&clkc CLKID_CPUCLK>; 54 #cooling-cells = <2>; /* min followed by max */ 55 }; 56 57 cpu3: cpu@203 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a5"; 60 next-level-cache = <&L2>; 61 reg = <0x203>; 62 enable-method = "amlogic,meson8b-smp"; 63 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; 64 operating-points-v2 = <&cpu_opp_table>; 65 clocks = <&clkc CLKID_CPUCLK>; 66 #cooling-cells = <2>; /* min followed by max */ 67 }; 68 }; 69 70 cpu_opp_table: opp-table { 71 compatible = "operating-points-v2"; 72 opp-shared; 73 74 opp-96000000 { 75 opp-hz = /bits/ 64 <96000000>; 76 opp-microvolt = <860000>; 77 }; 78 opp-192000000 { 79 opp-hz = /bits/ 64 <192000000>; 80 opp-microvolt = <860000>; 81 }; 82 opp-312000000 { 83 opp-hz = /bits/ 64 <312000000>; 84 opp-microvolt = <860000>; 85 }; 86 opp-408000000 { 87 opp-hz = /bits/ 64 <408000000>; 88 opp-microvolt = <860000>; 89 }; 90 opp-504000000 { 91 opp-hz = /bits/ 64 <504000000>; 92 opp-microvolt = <860000>; 93 }; 94 opp-600000000 { 95 opp-hz = /bits/ 64 <600000000>; 96 opp-microvolt = <860000>; 97 }; 98 opp-720000000 { 99 opp-hz = /bits/ 64 <720000000>; 100 opp-microvolt = <860000>; 101 }; 102 opp-816000000 { 103 opp-hz = /bits/ 64 <816000000>; 104 opp-microvolt = <900000>; 105 }; 106 opp-1008000000 { 107 opp-hz = /bits/ 64 <1008000000>; 108 opp-microvolt = <1140000>; 109 }; 110 opp-1200000000 { 111 opp-hz = /bits/ 64 <1200000000>; 112 opp-microvolt = <1140000>; 113 }; 114 opp-1320000000 { 115 opp-hz = /bits/ 64 <1320000000>; 116 opp-microvolt = <1140000>; 117 }; 118 opp-1488000000 { 119 opp-hz = /bits/ 64 <1488000000>; 120 opp-microvolt = <1140000>; 121 }; 122 opp-1536000000 { 123 opp-hz = /bits/ 64 <1536000000>; 124 opp-microvolt = <1140000>; 125 }; 126 }; 127 128 gpu_opp_table: opp-table-gpu { 129 compatible = "operating-points-v2"; 130 131 opp-255000000 { 132 opp-hz = /bits/ 64 <255000000>; 133 opp-microvolt = <1100000>; 134 }; 135 opp-364285714 { 136 opp-hz = /bits/ 64 <364285714>; 137 opp-microvolt = <1100000>; 138 }; 139 opp-425000000 { 140 opp-hz = /bits/ 64 <425000000>; 141 opp-microvolt = <1100000>; 142 }; 143 opp-510000000 { 144 opp-hz = /bits/ 64 <510000000>; 145 opp-microvolt = <1100000>; 146 }; 147 opp-637500000 { 148 opp-hz = /bits/ 64 <637500000>; 149 opp-microvolt = <1100000>; 150 turbo-mode; 151 }; 152 }; 153 154 pmu { 155 compatible = "arm,cortex-a5-pmu"; 156 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 160 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 161 }; 162 163 reserved-memory { 164 #address-cells = <1>; 165 #size-cells = <1>; 166 ranges; 167 168 /* 2 MiB reserved for Hardware ROM Firmware? */ 169 hwrom@0 { 170 reg = <0x0 0x200000>; 171 no-map; 172 }; 173 }; 174 175 thermal-zones { 176 soc-thermal { 177 polling-delay-passive = <250>; /* milliseconds */ 178 polling-delay = <1000>; /* milliseconds */ 179 thermal-sensors = <&thermal_sensor>; 180 181 cooling-maps { 182 map0 { 183 trip = <&soc_passive>; 184 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 185 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 186 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 187 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 188 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 189 }; 190 191 map1 { 192 trip = <&soc_hot>; 193 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 194 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 195 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 196 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 197 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 198 }; 199 }; 200 201 trips { 202 soc_passive: soc-passive { 203 temperature = <80000>; /* millicelsius */ 204 hysteresis = <2000>; /* millicelsius */ 205 type = "passive"; 206 }; 207 208 soc_hot: soc-hot { 209 temperature = <90000>; /* millicelsius */ 210 hysteresis = <2000>; /* millicelsius */ 211 type = "hot"; 212 }; 213 214 soc_critical: soc-critical { 215 temperature = <110000>; /* millicelsius */ 216 hysteresis = <2000>; /* millicelsius */ 217 type = "critical"; 218 }; 219 }; 220 }; 221 }; 222 223 mmcbus: bus@c8000000 { 224 compatible = "simple-bus"; 225 reg = <0xc8000000 0x8000>; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 ranges = <0x0 0xc8000000 0x8000>; 229 230 ddr_clkc: clock-controller@400 { 231 compatible = "amlogic,meson8b-ddr-clkc"; 232 reg = <0x400 0x20>; 233 clocks = <&xtal>; 234 clock-names = "xtal"; 235 #clock-cells = <1>; 236 }; 237 238 dmcbus: bus@6000 { 239 compatible = "simple-bus"; 240 reg = <0x6000 0x400>; 241 #address-cells = <1>; 242 #size-cells = <1>; 243 ranges = <0x0 0x6000 0x400>; 244 245 canvas: video-lut@48 { 246 compatible = "amlogic,meson8b-canvas", 247 "amlogic,canvas"; 248 reg = <0x48 0x14>; 249 }; 250 }; 251 }; 252 253 apb: bus@d0000000 { 254 compatible = "simple-bus"; 255 reg = <0xd0000000 0x200000>; 256 #address-cells = <1>; 257 #size-cells = <1>; 258 ranges = <0x0 0xd0000000 0x200000>; 259 260 mali: gpu@c0000 { 261 compatible = "amlogic,meson8b-mali", "arm,mali-450"; 262 reg = <0xc0000 0x40000>; 263 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 271 interrupt-names = "gp", "gpmmu", "pp", "pmu", 272 "pp0", "ppmmu0", "pp1", "ppmmu1"; 273 resets = <&reset RESET_MALI>; 274 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; 275 clock-names = "bus", "core"; 276 operating-points-v2 = <&gpu_opp_table>; 277 #cooling-cells = <2>; /* min followed by max */ 278 }; 279 }; 280}; /* end of / */ 281 282&aiu { 283 compatible = "amlogic,aiu-meson8b", "amlogic,aiu"; 284 clocks = <&clkc CLKID_AIU_GLUE>, 285 <&clkc CLKID_I2S_OUT>, 286 <&clkc CLKID_AOCLK_GATE>, 287 <&clkc CLKID_CTS_AMCLK>, 288 <&clkc CLKID_MIXER_IFACE>, 289 <&clkc CLKID_IEC958>, 290 <&clkc CLKID_IEC958_GATE>, 291 <&clkc CLKID_CTS_MCLK_I958>, 292 <&clkc CLKID_CTS_I958>; 293 clock-names = "pclk", 294 "i2s_pclk", 295 "i2s_aoclk", 296 "i2s_mclk", 297 "i2s_mixer", 298 "spdif_pclk", 299 "spdif_aoclk", 300 "spdif_mclk", 301 "spdif_mclk_sel"; 302 resets = <&reset RESET_AIU>; 303}; 304 305&aobus { 306 pmu: pmu@e0 { 307 compatible = "amlogic,meson8b-pmu", "syscon"; 308 reg = <0xe0 0x18>; 309 }; 310 311 pinctrl_aobus: pinctrl@14 { 312 compatible = "amlogic,meson8b-aobus-pinctrl"; 313 #address-cells = <1>; 314 #size-cells = <1>; 315 ranges = <0x0 0x14 0x1c>; 316 317 gpio_ao: bank@0 { 318 reg = <0x0 0x4>, 319 <0x18 0x4>, 320 <0x10 0x8>; 321 reg-names = "mux", "pull", "gpio"; 322 gpio-controller; 323 #gpio-cells = <2>; 324 gpio-ranges = <&pinctrl_aobus 0 0 16>; 325 }; 326 327 i2s_am_clk_pins: i2s-am-clk-out { 328 mux { 329 groups = "i2s_am_clk_out"; 330 function = "i2s"; 331 bias-disable; 332 }; 333 }; 334 335 i2s_out_ao_clk_pins: i2s-ao-clk-out { 336 mux { 337 groups = "i2s_ao_clk_out"; 338 function = "i2s"; 339 bias-disable; 340 }; 341 }; 342 343 i2s_out_lr_clk_pins: i2s-lr-clk-out { 344 mux { 345 groups = "i2s_lr_clk_out"; 346 function = "i2s"; 347 bias-disable; 348 }; 349 }; 350 351 i2s_out_ch01_ao_pins: i2s-out-ch01 { 352 mux { 353 groups = "i2s_out_01"; 354 function = "i2s"; 355 bias-disable; 356 }; 357 }; 358 359 spdif_out_1_pins: spdif-out-1 { 360 mux { 361 groups = "spdif_out_1"; 362 function = "spdif_1"; 363 bias-disable; 364 }; 365 }; 366 367 uart_ao_a_pins: uart_ao_a { 368 mux { 369 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 370 function = "uart_ao"; 371 bias-disable; 372 }; 373 }; 374 375 ir_recv_pins: remote { 376 mux { 377 groups = "remote_input"; 378 function = "remote"; 379 bias-disable; 380 }; 381 }; 382 }; 383}; 384 385&ao_arc_rproc { 386 compatible = "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc"; 387 amlogic,secbus2 = <&secbus2>; 388 sram = <&ao_arc_sram>; 389 resets = <&reset RESET_MEDIA_CPU>; 390 clocks = <&clkc CLKID_AO_MEDIA_CPU>; 391}; 392 393&cbus { 394 reset: reset-controller@4404 { 395 compatible = "amlogic,meson8b-reset"; 396 reg = <0x4404 0x9c>; 397 #reset-cells = <1>; 398 }; 399 400 analog_top: analog-top@81a8 { 401 compatible = "amlogic,meson8b-analog-top", "syscon"; 402 reg = <0x81a8 0x14>; 403 }; 404 405 pwm_ef: pwm@86c0 { 406 compatible = "amlogic,meson8b-pwm"; 407 reg = <0x86c0 0x10>; 408 #pwm-cells = <3>; 409 status = "disabled"; 410 }; 411 412 clock-measure@8758 { 413 compatible = "amlogic,meson8b-clk-measure"; 414 reg = <0x8758 0x1c>; 415 }; 416 417 pinctrl_cbus: pinctrl@8030 { 418 compatible = "amlogic,meson8b-cbus-pinctrl"; 419 #address-cells = <1>; 420 #size-cells = <1>; 421 ranges = <0x0 0x8030 0x108>; 422 423 gpio: bank@80 { 424 reg = <0x80 0x28>, 425 <0xb8 0x18>, 426 <0xf0 0x18>, 427 <0x00 0x38>; 428 reg-names = "mux", "pull", "pull-enable", "gpio"; 429 gpio-controller; 430 #gpio-cells = <2>; 431 gpio-ranges = <&pinctrl_cbus 0 0 83>; 432 }; 433 434 eth_rgmii_pins: eth-rgmii { 435 mux { 436 groups = "eth_tx_clk", 437 "eth_tx_en", 438 "eth_txd1_0", 439 "eth_txd0_0", 440 "eth_rx_clk", 441 "eth_rx_dv", 442 "eth_rxd1", 443 "eth_rxd0", 444 "eth_mdio_en", 445 "eth_mdc", 446 "eth_ref_clk", 447 "eth_txd2", 448 "eth_txd3", 449 "eth_rxd3", 450 "eth_rxd2"; 451 function = "ethernet"; 452 bias-disable; 453 }; 454 }; 455 456 eth_rmii_pins: eth-rmii { 457 mux { 458 groups = "eth_tx_en", 459 "eth_txd1_0", 460 "eth_txd0_0", 461 "eth_rx_clk", 462 "eth_rx_dv", 463 "eth_rxd1", 464 "eth_rxd0", 465 "eth_mdio_en", 466 "eth_mdc"; 467 function = "ethernet"; 468 bias-disable; 469 }; 470 }; 471 472 i2c_a_pins: i2c-a { 473 mux { 474 groups = "i2c_sda_a", "i2c_sck_a"; 475 function = "i2c_a"; 476 bias-disable; 477 }; 478 }; 479 480 sd_b_pins: sd-b { 481 mux { 482 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", 483 "sd_d3_b", "sd_clk_b", "sd_cmd_b"; 484 function = "sd_b"; 485 bias-disable; 486 }; 487 }; 488 489 sdxc_c_pins: sdxc-c { 490 mux { 491 groups = "sdxc_d0_c", "sdxc_d13_c", 492 "sdxc_d47_c", "sdxc_clk_c", 493 "sdxc_cmd_c"; 494 function = "sdxc_c"; 495 bias-pull-up; 496 }; 497 }; 498 499 pwm_c1_pins: pwm-c1 { 500 mux { 501 groups = "pwm_c1"; 502 function = "pwm_c"; 503 bias-disable; 504 }; 505 }; 506 507 pwm_d_pins: pwm-d { 508 mux { 509 groups = "pwm_d"; 510 function = "pwm_d"; 511 bias-disable; 512 }; 513 }; 514 515 uart_b0_pins: uart-b0 { 516 mux { 517 groups = "uart_tx_b0", 518 "uart_rx_b0"; 519 function = "uart_b"; 520 bias-disable; 521 }; 522 }; 523 524 uart_b0_cts_rts_pins: uart-b0-cts-rts { 525 mux { 526 groups = "uart_cts_b0", 527 "uart_rts_b0"; 528 function = "uart_b"; 529 bias-disable; 530 }; 531 }; 532 }; 533}; 534 535&ahb_sram { 536 ao_arc_sram: aoarc-sram@0 { 537 compatible = "amlogic,meson8b-ao-arc-sram"; 538 reg = <0x0 0x8000>; 539 pool; 540 }; 541 542 smp-sram@1ff80 { 543 compatible = "amlogic,meson8b-smp-sram"; 544 reg = <0x1ff80 0x8>; 545 }; 546}; 547 548 549&efuse { 550 compatible = "amlogic,meson8b-efuse"; 551 clocks = <&clkc CLKID_EFUSE>; 552 clock-names = "core"; 553 554 temperature_calib: calib@1f4 { 555 /* only the upper two bytes are relevant */ 556 reg = <0x1f4 0x4>; 557 }; 558}; 559 560ðmac { 561 compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac"; 562 563 reg = <0xc9410000 0x10000 564 0xc1108140 0x4>; 565 566 clocks = <&clkc CLKID_ETH>, 567 <&clkc CLKID_MPLL2>, 568 <&clkc CLKID_MPLL2>, 569 <&clkc CLKID_FCLK_DIV2>; 570 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; 571 rx-fifo-depth = <4096>; 572 tx-fifo-depth = <2048>; 573 574 resets = <&reset RESET_ETHERNET>; 575 reset-names = "stmmaceth"; 576 577 power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; 578}; 579 580&gpio_intc { 581 compatible = "amlogic,meson8b-gpio-intc", 582 "amlogic,meson-gpio-intc"; 583 status = "okay"; 584}; 585 586&hhi { 587 clkc: clock-controller { 588 compatible = "amlogic,meson8b-clkc"; 589 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; 590 clock-names = "xtal", "ddr_pll"; 591 #clock-cells = <1>; 592 #reset-cells = <1>; 593 }; 594 595 pwrc: power-controller { 596 compatible = "amlogic,meson8b-pwrc"; 597 #power-domain-cells = <1>; 598 amlogic,ao-sysctrl = <&pmu>; 599 resets = <&reset RESET_DBLK>, 600 <&reset RESET_PIC_DC>, 601 <&reset RESET_HDMI_APB>, 602 <&reset RESET_HDMI_SYSTEM_RESET>, 603 <&reset RESET_VENCI>, 604 <&reset RESET_VENCP>, 605 <&reset RESET_VDAC_4>, 606 <&reset RESET_VENCL>, 607 <&reset RESET_VIU>, 608 <&reset RESET_VENC>, 609 <&reset RESET_RDMA>; 610 reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", 611 "venci", "vencp", "vdac", "vencl", "viu", 612 "venc", "rdma"; 613 clocks = <&clkc CLKID_VPU>; 614 clock-names = "vpu"; 615 assigned-clocks = <&clkc CLKID_VPU>; 616 assigned-clock-rates = <182142857>; 617 }; 618}; 619 620&hwrng { 621 clocks = <&clkc CLKID_RNG0>; 622 clock-names = "core"; 623}; 624 625&i2c_AO { 626 clocks = <&clkc CLKID_CLK81>; 627}; 628 629&i2c_A { 630 clocks = <&clkc CLKID_I2C>; 631}; 632 633&i2c_B { 634 clocks = <&clkc CLKID_I2C>; 635}; 636 637&L2 { 638 arm,data-latency = <3 3 3>; 639 arm,tag-latency = <2 2 2>; 640 arm,filter-ranges = <0x100000 0xc0000000>; 641 prefetch-data = <1>; 642 prefetch-instr = <1>; 643 arm,prefetch-offset = <7>; 644 arm,double-linefill = <1>; 645 arm,prefetch-drop = <1>; 646 arm,shared-override; 647}; 648 649&periph { 650 scu@0 { 651 compatible = "arm,cortex-a5-scu"; 652 reg = <0x0 0x100>; 653 }; 654 655 timer@200 { 656 compatible = "arm,cortex-a5-global-timer"; 657 reg = <0x200 0x20>; 658 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 659 clocks = <&clkc CLKID_PERIPH>; 660 661 /* 662 * the arm_global_timer driver currently does not handle clock 663 * rate changes. Keep it disabled for now. 664 */ 665 status = "disabled"; 666 }; 667 668 timer@600 { 669 compatible = "arm,cortex-a5-twd-timer"; 670 reg = <0x600 0x20>; 671 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 672 clocks = <&clkc CLKID_PERIPH>; 673 }; 674}; 675 676&pwm_ab { 677 compatible = "amlogic,meson8b-pwm"; 678}; 679 680&pwm_cd { 681 compatible = "amlogic,meson8b-pwm"; 682}; 683 684&rtc { 685 compatible = "amlogic,meson8b-rtc"; 686 resets = <&reset RESET_RTC>; 687}; 688 689&saradc { 690 compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; 691 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; 692 clock-names = "clkin", "core"; 693 amlogic,hhi-sysctrl = <&hhi>; 694 nvmem-cells = <&temperature_calib>; 695 nvmem-cell-names = "temperature_calib"; 696}; 697 698&sdhc { 699 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; 700 clocks = <&xtal>, 701 <&clkc CLKID_FCLK_DIV4>, 702 <&clkc CLKID_FCLK_DIV3>, 703 <&clkc CLKID_FCLK_DIV5>, 704 <&clkc CLKID_SDHC>; 705 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; 706}; 707 708&secbus { 709 secbus2: system-controller@4000 { 710 compatible = "amlogic,meson8b-secbus2", "syscon"; 711 reg = <0x4000 0x2000>; 712 }; 713}; 714 715&sdio { 716 compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; 717 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; 718 clock-names = "core", "clkin"; 719}; 720 721&timer_abcde { 722 clocks = <&xtal>, <&clkc CLKID_CLK81>; 723 clock-names = "xtal", "pclk"; 724}; 725 726&uart_AO { 727 compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart"; 728 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>; 729 clock-names = "xtal", "pclk", "baud"; 730}; 731 732&uart_A { 733 compatible = "amlogic,meson8b-uart"; 734 clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; 735 clock-names = "xtal", "pclk", "baud"; 736}; 737 738&uart_B { 739 compatible = "amlogic,meson8b-uart"; 740 clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>; 741 clock-names = "xtal", "pclk", "baud"; 742}; 743 744&uart_C { 745 compatible = "amlogic,meson8b-uart"; 746 clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>; 747 clock-names = "xtal", "pclk", "baud"; 748}; 749 750&usb0 { 751 compatible = "amlogic,meson8b-usb", "snps,dwc2"; 752 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 753 clock-names = "otg"; 754}; 755 756&usb1 { 757 compatible = "amlogic,meson8b-usb", "snps,dwc2"; 758 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 759 clock-names = "otg"; 760}; 761 762&usb0_phy { 763 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; 764 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 765 clock-names = "usb_general", "usb"; 766 resets = <&reset RESET_USB_OTG>; 767}; 768 769&usb1_phy { 770 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; 771 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 772 clock-names = "usb_general", "usb"; 773 resets = <&reset RESET_USB_OTG>; 774}; 775 776&wdt { 777 compatible = "amlogic,meson8b-wdt"; 778}; 779