1// SPDX-License-Identifier: (GPL-2.0+ OR X11) 2/* 3 * Copyright 2018 Icenowy Zheng <icenowy@aosc.io> 4 * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com> 5 */ 6 7#include <dt-bindings/clock/suniv-ccu-f1c100s.h> 8#include <dt-bindings/reset/suniv-ccu-f1c100s.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 interrupt-parent = <&intc>; 14 15 clocks { 16 osc24M: clk-24M { 17 #clock-cells = <0>; 18 compatible = "fixed-clock"; 19 clock-frequency = <24000000>; 20 clock-output-names = "osc24M"; 21 }; 22 23 osc32k: clk-32k { 24 #clock-cells = <0>; 25 compatible = "fixed-clock"; 26 clock-frequency = <32768>; 27 clock-output-names = "osc32k"; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu@0 { 36 compatible = "arm,arm926ej-s"; 37 device_type = "cpu"; 38 reg = <0x0>; 39 }; 40 }; 41 42 soc { 43 compatible = "simple-bus"; 44 #address-cells = <1>; 45 #size-cells = <1>; 46 ranges; 47 48 sram-controller@1c00000 { 49 compatible = "allwinner,suniv-f1c100s-system-control", 50 "allwinner,sun4i-a10-system-control"; 51 reg = <0x01c00000 0x30>; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 ranges; 55 56 sram_d: sram@10000 { 57 compatible = "mmio-sram"; 58 reg = <0x00010000 0x1000>; 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges = <0 0x00010000 0x1000>; 62 63 otg_sram: sram-section@0 { 64 compatible = "allwinner,suniv-f1c100s-sram-d", 65 "allwinner,sun4i-a10-sram-d"; 66 reg = <0x0000 0x1000>; 67 status = "disabled"; 68 }; 69 }; 70 }; 71 72 spi0: spi@1c05000 { 73 compatible = "allwinner,suniv-f1c100s-spi", 74 "allwinner,sun8i-h3-spi"; 75 reg = <0x01c05000 0x1000>; 76 interrupts = <10>; 77 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>; 78 clock-names = "ahb", "mod"; 79 resets = <&ccu RST_BUS_SPI0>; 80 status = "disabled"; 81 num-cs = <1>; 82 #address-cells = <1>; 83 #size-cells = <0>; 84 }; 85 86 spi1: spi@1c06000 { 87 compatible = "allwinner,suniv-f1c100s-spi", 88 "allwinner,sun8i-h3-spi"; 89 reg = <0x01c06000 0x1000>; 90 interrupts = <11>; 91 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>; 92 clock-names = "ahb", "mod"; 93 resets = <&ccu RST_BUS_SPI1>; 94 status = "disabled"; 95 num-cs = <1>; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 }; 99 100 mmc0: mmc@1c0f000 { 101 compatible = "allwinner,suniv-f1c100s-mmc", 102 "allwinner,sun7i-a20-mmc"; 103 reg = <0x01c0f000 0x1000>; 104 clocks = <&ccu CLK_BUS_MMC0>, 105 <&ccu CLK_MMC0>, 106 <&ccu CLK_MMC0_OUTPUT>, 107 <&ccu CLK_MMC0_SAMPLE>; 108 clock-names = "ahb", "mmc", "output", "sample"; 109 resets = <&ccu RST_BUS_MMC0>; 110 reset-names = "ahb"; 111 interrupts = <23>; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&mmc0_pins>; 114 status = "disabled"; 115 #address-cells = <1>; 116 #size-cells = <0>; 117 }; 118 119 mmc1: mmc@1c10000 { 120 compatible = "allwinner,suniv-f1c100s-mmc", 121 "allwinner,sun7i-a20-mmc"; 122 reg = <0x01c10000 0x1000>; 123 clocks = <&ccu CLK_BUS_MMC1>, 124 <&ccu CLK_MMC1>, 125 <&ccu CLK_MMC1_OUTPUT>, 126 <&ccu CLK_MMC1_SAMPLE>; 127 clock-names = "ahb", "mmc", "output", "sample"; 128 resets = <&ccu RST_BUS_MMC1>; 129 reset-names = "ahb"; 130 interrupts = <24>; 131 status = "disabled"; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 }; 135 136 usb_otg: usb@1c13000 { 137 compatible = "allwinner,suniv-f1c100s-musb"; 138 reg = <0x01c13000 0x0400>; 139 clocks = <&ccu CLK_BUS_OTG>; 140 resets = <&ccu RST_BUS_OTG>; 141 interrupts = <26>; 142 interrupt-names = "mc"; 143 phys = <&usbphy 0>; 144 phy-names = "usb"; 145 extcon = <&usbphy 0>; 146 allwinner,sram = <&otg_sram 1>; 147 status = "disabled"; 148 }; 149 150 usbphy: phy@1c13400 { 151 compatible = "allwinner,suniv-f1c100s-usb-phy"; 152 reg = <0x01c13400 0x10>; 153 reg-names = "phy_ctrl"; 154 clocks = <&ccu CLK_USB_PHY0>; 155 clock-names = "usb0_phy"; 156 resets = <&ccu RST_USB_PHY0>; 157 reset-names = "usb0_reset"; 158 #phy-cells = <1>; 159 status = "disabled"; 160 }; 161 162 ccu: clock@1c20000 { 163 compatible = "allwinner,suniv-f1c100s-ccu"; 164 reg = <0x01c20000 0x400>; 165 clocks = <&osc24M>, <&osc32k>; 166 clock-names = "hosc", "losc"; 167 #clock-cells = <1>; 168 #reset-cells = <1>; 169 }; 170 171 intc: interrupt-controller@1c20400 { 172 compatible = "allwinner,suniv-f1c100s-ic"; 173 reg = <0x01c20400 0x400>; 174 interrupt-controller; 175 #interrupt-cells = <1>; 176 }; 177 178 pio: pinctrl@1c20800 { 179 compatible = "allwinner,suniv-f1c100s-pinctrl"; 180 reg = <0x01c20800 0x400>; 181 interrupts = <38>, <39>, <40>; 182 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; 183 clock-names = "apb", "hosc", "losc"; 184 gpio-controller; 185 interrupt-controller; 186 #interrupt-cells = <3>; 187 #gpio-cells = <3>; 188 189 mmc0_pins: mmc0-pins { 190 pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; 191 function = "mmc0"; 192 drive-strength = <30>; 193 }; 194 195 /omit-if-no-ref/ 196 i2c0_pd_pins: i2c0-pd-pins { 197 pins = "PD0", "PD12"; 198 function = "i2c0"; 199 }; 200 201 spi0_pc_pins: spi0-pc-pins { 202 pins = "PC0", "PC1", "PC2", "PC3"; 203 function = "spi0"; 204 }; 205 206 uart0_pe_pins: uart0-pe-pins { 207 pins = "PE0", "PE1"; 208 function = "uart0"; 209 }; 210 211 /omit-if-no-ref/ 212 uart1_pa_pins: uart1-pa-pins { 213 pins = "PA2", "PA3"; 214 function = "uart1"; 215 }; 216 }; 217 218 i2c0: i2c@1c27000 { 219 compatible = "allwinner,suniv-f1c100s-i2c", 220 "allwinner,sun6i-a31-i2c"; 221 reg = <0x01c27000 0x400>; 222 interrupts = <7>; 223 clocks = <&ccu CLK_BUS_I2C0>; 224 resets = <&ccu RST_BUS_I2C0>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 status = "disabled"; 228 }; 229 230 i2c1: i2c@1c27400 { 231 compatible = "allwinner,suniv-f1c100s-i2c", 232 "allwinner,sun6i-a31-i2c"; 233 reg = <0x01c27400 0x400>; 234 interrupts = <8>; 235 clocks = <&ccu CLK_BUS_I2C1>; 236 resets = <&ccu RST_BUS_I2C1>; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 status = "disabled"; 240 }; 241 242 i2c2: i2c@1c27800 { 243 compatible = "allwinner,suniv-f1c100s-i2c", 244 "allwinner,sun6i-a31-i2c"; 245 reg = <0x01c27800 0x400>; 246 interrupts = <9>; 247 clocks = <&ccu CLK_BUS_I2C2>; 248 resets = <&ccu RST_BUS_I2C2>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 status = "disabled"; 252 }; 253 254 timer@1c20c00 { 255 compatible = "allwinner,suniv-f1c100s-timer"; 256 reg = <0x01c20c00 0x90>; 257 interrupts = <13>, <14>, <15>; 258 clocks = <&osc24M>; 259 }; 260 261 wdt: watchdog@1c20ca0 { 262 compatible = "allwinner,suniv-f1c100s-wdt", 263 "allwinner,sun6i-a31-wdt"; 264 reg = <0x01c20ca0 0x20>; 265 interrupts = <16>; 266 clocks = <&osc32k>; 267 }; 268 269 pwm: pwm@1c21000 { 270 compatible = "allwinner,suniv-f1c100s-pwm", 271 "allwinner,sun7i-a20-pwm"; 272 reg = <0x01c21000 0x400>; 273 clocks = <&osc24M>; 274 #pwm-cells = <3>; 275 status = "disabled"; 276 }; 277 278 ir: ir@1c22c00 { 279 compatible = "allwinner,suniv-f1c100s-ir", 280 "allwinner,sun6i-a31-ir"; 281 reg = <0x01c22c00 0x400>; 282 clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>; 283 clock-names = "apb", "ir"; 284 resets = <&ccu RST_BUS_IR>; 285 interrupts = <6>; 286 status = "disabled"; 287 }; 288 289 lradc: lradc@1c23400 { 290 compatible = "allwinner,suniv-f1c100s-lradc", 291 "allwinner,sun8i-a83t-r-lradc"; 292 reg = <0x01c23400 0x400>; 293 interrupts = <22>; 294 status = "disabled"; 295 }; 296 297 uart0: serial@1c25000 { 298 compatible = "snps,dw-apb-uart"; 299 reg = <0x01c25000 0x400>; 300 interrupts = <1>; 301 reg-shift = <2>; 302 reg-io-width = <4>; 303 clocks = <&ccu CLK_BUS_UART0>; 304 resets = <&ccu RST_BUS_UART0>; 305 status = "disabled"; 306 }; 307 308 uart1: serial@1c25400 { 309 compatible = "snps,dw-apb-uart"; 310 reg = <0x01c25400 0x400>; 311 interrupts = <2>; 312 reg-shift = <2>; 313 reg-io-width = <4>; 314 clocks = <&ccu CLK_BUS_UART1>; 315 resets = <&ccu RST_BUS_UART1>; 316 status = "disabled"; 317 }; 318 319 uart2: serial@1c25800 { 320 compatible = "snps,dw-apb-uart"; 321 reg = <0x01c25800 0x400>; 322 interrupts = <3>; 323 reg-shift = <2>; 324 reg-io-width = <4>; 325 clocks = <&ccu CLK_BUS_UART2>; 326 resets = <&ccu RST_BUS_UART2>; 327 status = "disabled"; 328 }; 329 }; 330}; 331