xref: /linux/scripts/dtc/include-prefixes/arc/skeleton_hs_idu.dtsi (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
4 */
5
6/ {
7	compatible = "snps,arc";
8	#address-cells = <1>;
9	#size-cells = <1>;
10	chosen { };
11	aliases { };
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "snps,archs38";
20			reg = <0>;
21			clocks = <&core_clk>;
22		};
23		cpu@1 {
24			device_type = "cpu";
25			compatible = "snps,archs38";
26			reg = <1>;
27			clocks = <&core_clk>;
28		};
29		cpu@2 {
30			device_type = "cpu";
31			compatible = "snps,archs38";
32			reg = <2>;
33			clocks = <&core_clk>;
34		};
35		cpu@3 {
36			device_type = "cpu";
37			compatible = "snps,archs38";
38			reg = <3>;
39			clocks = <&core_clk>;
40		};
41	};
42
43	/* TIMER0 with interrupt for clockevent */
44	timer0 {
45		compatible = "snps,arc-timer";
46		interrupts = <16>;
47		interrupt-parent = <&core_intc>;
48		clocks = <&core_clk>;
49	};
50
51	/* 64-bit Global Free Running Counter */
52	gfrc {
53		compatible = "snps,archs-timer-gfrc";
54		clocks = <&core_clk>;
55	};
56
57	memory {
58		device_type = "memory";
59		reg = <0x80000000 0x10000000>;	/* 256M */
60	};
61};
62