1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Optimized xor_block operation for RAID4/5 4 * 5 * Copyright IBM Corp. 2016 6 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> 7 */ 8 9 #include <linux/types.h> 10 #include "xor_impl.h" 11 #include "xor_arch.h" 12 13 static void xor_xc_2(unsigned long bytes, unsigned long * __restrict p1, 14 const unsigned long * __restrict p2) 15 { 16 asm volatile( 17 " aghi %0,-1\n" 18 " jm 3f\n" 19 " srlg 0,%0,8\n" 20 " ltgr 0,0\n" 21 " jz 1f\n" 22 "0: xc 0(256,%1),0(%2)\n" 23 " la %1,256(%1)\n" 24 " la %2,256(%2)\n" 25 " brctg 0,0b\n" 26 "1: exrl %0,2f\n" 27 " j 3f\n" 28 "2: xc 0(1,%1),0(%2)\n" 29 "3:" 30 : "+a" (bytes), "+a" (p1), "+a" (p2) 31 : : "0", "cc", "memory"); 32 } 33 34 static void xor_xc_3(unsigned long bytes, unsigned long * __restrict p1, 35 const unsigned long * __restrict p2, 36 const unsigned long * __restrict p3) 37 { 38 asm volatile( 39 " aghi %0,-1\n" 40 " jm 4f\n" 41 " srlg 0,%0,8\n" 42 " ltgr 0,0\n" 43 " jz 1f\n" 44 "0: xc 0(256,%1),0(%2)\n" 45 " xc 0(256,%1),0(%3)\n" 46 " la %1,256(%1)\n" 47 " la %2,256(%2)\n" 48 " la %3,256(%3)\n" 49 " brctg 0,0b\n" 50 "1: exrl %0,2f\n" 51 " exrl %0,3f\n" 52 " j 4f\n" 53 "2: xc 0(1,%1),0(%2)\n" 54 "3: xc 0(1,%1),0(%3)\n" 55 "4:" 56 : "+a" (bytes), "+a" (p1), "+a" (p2), "+a" (p3) 57 : : "0", "cc", "memory"); 58 } 59 60 static void xor_xc_4(unsigned long bytes, unsigned long * __restrict p1, 61 const unsigned long * __restrict p2, 62 const unsigned long * __restrict p3, 63 const unsigned long * __restrict p4) 64 { 65 asm volatile( 66 " aghi %0,-1\n" 67 " jm 5f\n" 68 " srlg 0,%0,8\n" 69 " ltgr 0,0\n" 70 " jz 1f\n" 71 "0: xc 0(256,%1),0(%2)\n" 72 " xc 0(256,%1),0(%3)\n" 73 " xc 0(256,%1),0(%4)\n" 74 " la %1,256(%1)\n" 75 " la %2,256(%2)\n" 76 " la %3,256(%3)\n" 77 " la %4,256(%4)\n" 78 " brctg 0,0b\n" 79 "1: exrl %0,2f\n" 80 " exrl %0,3f\n" 81 " exrl %0,4f\n" 82 " j 5f\n" 83 "2: xc 0(1,%1),0(%2)\n" 84 "3: xc 0(1,%1),0(%3)\n" 85 "4: xc 0(1,%1),0(%4)\n" 86 "5:" 87 : "+a" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4) 88 : : "0", "cc", "memory"); 89 } 90 91 static void xor_xc_5(unsigned long bytes, unsigned long * __restrict p1, 92 const unsigned long * __restrict p2, 93 const unsigned long * __restrict p3, 94 const unsigned long * __restrict p4, 95 const unsigned long * __restrict p5) 96 { 97 asm volatile( 98 " aghi %0,-1\n" 99 " jm 6f\n" 100 " srlg 0,%0,8\n" 101 " ltgr 0,0\n" 102 " jz 1f\n" 103 "0: xc 0(256,%1),0(%2)\n" 104 " xc 0(256,%1),0(%3)\n" 105 " xc 0(256,%1),0(%4)\n" 106 " xc 0(256,%1),0(%5)\n" 107 " la %1,256(%1)\n" 108 " la %2,256(%2)\n" 109 " la %3,256(%3)\n" 110 " la %4,256(%4)\n" 111 " la %5,256(%5)\n" 112 " brctg 0,0b\n" 113 "1: exrl %0,2f\n" 114 " exrl %0,3f\n" 115 " exrl %0,4f\n" 116 " exrl %0,5f\n" 117 " j 6f\n" 118 "2: xc 0(1,%1),0(%2)\n" 119 "3: xc 0(1,%1),0(%3)\n" 120 "4: xc 0(1,%1),0(%4)\n" 121 "5: xc 0(1,%1),0(%5)\n" 122 "6:" 123 : "+a" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4), 124 "+a" (p5) 125 : : "0", "cc", "memory"); 126 } 127 128 DO_XOR_BLOCKS(xc, xor_xc_2, xor_xc_3, xor_xc_4, xor_xc_5); 129 130 struct xor_block_template xor_block_xc = { 131 .name = "xc", 132 .xor_gen = xor_gen_xc, 133 }; 134