1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Early sched_ext type definitions. 4 * 5 * Copyright (c) 2026 Meta Platforms, Inc. and affiliates. 6 * Copyright (c) 2026 Tejun Heo <tj@kernel.org> 7 */ 8 #ifndef _KERNEL_SCHED_EXT_TYPES_H 9 #define _KERNEL_SCHED_EXT_TYPES_H 10 11 #include <linux/types.h> 12 #include <linux/jiffies.h> 13 #include <linux/overflow.h> 14 #include <linux/time64.h> 15 #include <linux/sched/topology.h> 16 17 enum scx_consts { 18 SCX_DSP_DFL_MAX_BATCH = 32, 19 SCX_DSP_MAX_LOOPS = 32, 20 SCX_WATCHDOG_MAX_TIMEOUT = 30 * HZ, 21 22 /* per-CPU chunk size for p->scx.tid allocation, see scx_alloc_tid() */ 23 SCX_TID_CHUNK = 1024, 24 25 SCX_EXIT_BT_LEN = 64, 26 SCX_EXIT_MSG_LEN = 1024, 27 SCX_EXIT_DUMP_DFL_LEN = 32768, 28 29 SCX_CPUPERF_ONE = SCHED_CAPACITY_SCALE, 30 31 /* 32 * Iterating all tasks may take a while. Periodically drop 33 * scx_tasks_lock to avoid causing e.g. CSD and RCU stalls. 34 */ 35 SCX_TASK_ITER_BATCH = 32, 36 37 SCX_BYPASS_HOST_NTH = 2, 38 39 SCX_BYPASS_LB_DFL_INTV_US = 500 * USEC_PER_MSEC, 40 SCX_BYPASS_LB_DONOR_PCT = 125, 41 SCX_BYPASS_LB_MIN_DELTA_DIV = 4, 42 SCX_BYPASS_LB_BATCH = 256, 43 44 SCX_REENQ_LOCAL_MAX_REPEAT = 256, 45 46 SCX_SUB_MAX_DEPTH = 4, 47 }; 48 49 /* 50 * Per-cid topology info. For each topology level (core, LLC, node), records 51 * the first cid in the unit and its global index. Global indices are 52 * consecutive integers assigned in cid-walk order, so e.g. core_idx ranges 53 * over [0, nr_cores_at_init) with no gaps. No-topo cids have all fields set 54 * to -1. 55 * 56 * @core_cid: first cid of this cid's core (smt-sibling group) 57 * @core_idx: global index of that core, in [0, nr_cores_at_init) 58 * @llc_cid: first cid of this cid's LLC 59 * @llc_idx: global index of that LLC, in [0, nr_llcs_at_init) 60 * @node_cid: first cid of this cid's NUMA node 61 * @node_idx: global index of that node, in [0, nr_nodes_at_init) 62 */ 63 struct scx_cid_topo { 64 s32 core_cid; 65 s32 core_idx; 66 s32 llc_cid; 67 s32 llc_idx; 68 s32 node_cid; 69 s32 node_idx; 70 }; 71 72 /* 73 * cmask: variable-length, base-windowed bitmap over cid space 74 * ----------------------------------------------------------- 75 * 76 * A cmask covers the cid range [base, base + nr_cids). bits[] is aligned to the 77 * global 64-cid grid: bits[0] spans [base & ~63, (base & ~63) + 64), so the 78 * first (base & 63) bits of bits[0] are head padding and the trailing bits of 79 * the last active word past base + nr_cids are tail padding. Both stay zero; 80 * all mutating helpers preserve that. Words past the last active word are not 81 * read by any helper and have no constraint. 82 * 83 * Grid alignment means two cmasks always address bits[] against the same global 84 * 64-cid windows, so cross-cmask word ops (AND, OR, ...) reduce to 85 * 86 * dst->bits[i] OP= src->bits[i - delta] 87 * 88 * with no bit-shifting, regardless of how the two bases relate mod 64. 89 */ 90 struct scx_cmask { 91 u32 base; 92 u32 nr_cids; 93 u32 alloc_words; 94 u64 bits[] __counted_by(alloc_words); 95 }; 96 97 /* 98 * Number of u64 words of bits[] storage that covers @nr_cids regardless of base 99 * alignment. The +1 absorbs up to 63 bits of head padding when base is not 100 * 64-aligned - always allocating one extra word beats branching on base or 101 * splitting the compute. The u64 cast keeps the +63 from wrapping when @nr_cids 102 * is near U32_MAX, so callers bounds-checking the result against @alloc_words 103 * catch the overflow instead of seeing a small value. 104 */ 105 #define SCX_CMASK_NR_WORDS(nr_cids) ((u32)(((u64)(nr_cids) + 63) / 64 + 1)) 106 107 /** 108 * __SCX_CMASK_DEFINE - Define an on-stack cmask with explicit storage capacity 109 * @NAME: variable name to define 110 * @BASE: first cid of the active range 111 * @NR_CIDS: active range length 112 * @ALLOC_CIDS: storage capacity in cids, at least @NR_CIDS 113 * 114 * @NAME aliases zero-initialized storage with the active range set to 115 * [BASE, BASE + NR_CIDS). Use scx_cmask_reframe() to reshape later, up to 116 * @ALLOC_CIDS. 117 */ 118 #define __SCX_CMASK_DEFINE(NAME, BASE, NR_CIDS, ALLOC_CIDS) \ 119 _DEFINE_FLEX(struct scx_cmask, NAME, bits, SCX_CMASK_NR_WORDS(ALLOC_CIDS), \ 120 = { .base = (BASE), \ 121 .nr_cids = (NR_CIDS), \ 122 .alloc_words = SCX_CMASK_NR_WORDS(ALLOC_CIDS) }) 123 124 /** 125 * SCX_CMASK_DEFINE - Define an on-stack cmask on tight storage 126 * @NAME: variable name to define 127 * @BASE: first cid of the active range 128 * @NR_CIDS: active range length, also storage capacity 129 * 130 * @NAME aliases zero-initialized storage with the active range and storage 131 * both [BASE, BASE + NR_CIDS). 132 */ 133 #define SCX_CMASK_DEFINE(NAME, BASE, NR_CIDS) \ 134 __SCX_CMASK_DEFINE(NAME, BASE, NR_CIDS, NR_CIDS) 135 136 /** 137 * SCX_CMASK_DEFINE_SHARD - Define an on-stack cmask sized to one shard 138 * @NAME: variable name to define 139 * @BASE: first cid of the active range 140 * @NR_CIDS: active range length, must be <= SCX_CID_SHARD_MAX_CPUS 141 * 142 * Storage is fixed at SCX_CID_SHARD_MAX_CPUS, active range framed by 143 * (BASE, NR_CIDS). Passing NR_CIDS > SCX_CID_SHARD_MAX_CPUS leaves the 144 * cmask claiming more bits than storage holds and subsequent cmask 145 * operations will overrun. 146 */ 147 #define SCX_CMASK_DEFINE_SHARD(NAME, BASE, NR_CIDS) \ 148 __SCX_CMASK_DEFINE(NAME, BASE, NR_CIDS, SCX_CID_SHARD_MAX_CPUS) 149 150 #endif /* _KERNEL_SCHED_EXT_TYPES_H */ 151