1ac0ffe7cSVladimir Oltean /* SPDX-License-Identifier: GPL-2.0+ */ 2ac0ffe7cSVladimir Oltean /* Copyright 2023-2026 NXP */ 3ac0ffe7cSVladimir Oltean 4ac0ffe7cSVladimir Oltean #ifndef __PHY_FSL_LYNX_H_ 5ac0ffe7cSVladimir Oltean #define __PHY_FSL_LYNX_H_ 6ac0ffe7cSVladimir Oltean 7ac0ffe7cSVladimir Oltean enum lynx_lane_mode { 8ac0ffe7cSVladimir Oltean LANE_MODE_UNKNOWN, 9ac0ffe7cSVladimir Oltean LANE_MODE_1000BASEX_SGMII, 10*6dc92ba4SVladimir Oltean LANE_MODE_2500BASEX, 11*6dc92ba4SVladimir Oltean LANE_MODE_QSGMII, 12*6dc92ba4SVladimir Oltean LANE_MODE_10G_QXGMII, 13ac0ffe7cSVladimir Oltean LANE_MODE_10GBASER, 14ac0ffe7cSVladimir Oltean LANE_MODE_USXGMII, 15ac0ffe7cSVladimir Oltean LANE_MODE_25GBASER, 16ac0ffe7cSVladimir Oltean LANE_MODE_MAX, 17ac0ffe7cSVladimir Oltean }; 18ac0ffe7cSVladimir Oltean 19*6dc92ba4SVladimir Oltean static inline bool lynx_lane_mode_uses_gmii_mac(enum lynx_lane_mode mode) 20*6dc92ba4SVladimir Oltean { 21*6dc92ba4SVladimir Oltean switch (mode) { 22*6dc92ba4SVladimir Oltean case LANE_MODE_1000BASEX_SGMII: 23*6dc92ba4SVladimir Oltean case LANE_MODE_2500BASEX: 24*6dc92ba4SVladimir Oltean case LANE_MODE_QSGMII: 25*6dc92ba4SVladimir Oltean case LANE_MODE_10G_QXGMII: 26*6dc92ba4SVladimir Oltean return true; 27*6dc92ba4SVladimir Oltean default: 28*6dc92ba4SVladimir Oltean return false; 29*6dc92ba4SVladimir Oltean } 30*6dc92ba4SVladimir Oltean } 31*6dc92ba4SVladimir Oltean 32*6dc92ba4SVladimir Oltean static inline bool lynx_lane_mode_uses_xgmii_mac(enum lynx_lane_mode mode) 33*6dc92ba4SVladimir Oltean { 34*6dc92ba4SVladimir Oltean switch (mode) { 35*6dc92ba4SVladimir Oltean case LANE_MODE_10GBASER: 36*6dc92ba4SVladimir Oltean case LANE_MODE_USXGMII: 37*6dc92ba4SVladimir Oltean return true; 38*6dc92ba4SVladimir Oltean default: 39*6dc92ba4SVladimir Oltean return false; 40*6dc92ba4SVladimir Oltean } 41*6dc92ba4SVladimir Oltean } 42*6dc92ba4SVladimir Oltean 43ac0ffe7cSVladimir Oltean #endif /* __PHY_FSL_LYNX_H_ */ 44