1 /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> 5 * Author: Joseph Chen <chenjh@rock-chips.com> 6 */ 7 8 #ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H 9 #define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H 10 11 #define SRST_CORE0_PO 0 12 #define SRST_CORE1_PO 1 13 #define SRST_CORE2_PO 2 14 #define SRST_CORE3_PO 3 15 #define SRST_CORE0 4 16 #define SRST_CORE1 5 17 #define SRST_CORE2 6 18 #define SRST_CORE3 7 19 #define SRST_NL2 8 20 #define SRST_CORE_BIU 9 21 #define SRST_CORE_CRYPTO 10 22 #define SRST_P_DBG 11 23 #define SRST_POT_DBG 12 24 #define SRST_NT_DBG 13 25 #define SRST_P_CORE_GRF 14 26 #define SRST_P_DAPLITE_BIU 15 27 #define SRST_P_CPU_BIU 16 28 #define SRST_REF_PVTPLL_CORE 17 29 #define SRST_A_BUS_VOPGL_BIU 18 30 #define SRST_A_BUS_H_BIU 19 31 #define SRST_A_SYSMEM_BIU 20 32 #define SRST_A_BUS_BIU 21 33 #define SRST_H_BUS_BIU 22 34 #define SRST_P_BUS_BIU 23 35 #define SRST_P_DFT2APB 24 36 #define SRST_P_BUS_GRF 25 37 #define SRST_A_BUS_M_BIU 26 38 #define SRST_A_GIC 27 39 #define SRST_A_SPINLOCK 28 40 #define SRST_A_DMAC 29 41 #define SRST_P_TIMER 30 42 #define SRST_TIMER0 31 43 #define SRST_TIMER1 32 44 #define SRST_TIMER2 33 45 #define SRST_TIMER3 34 46 #define SRST_TIMER4 35 47 #define SRST_TIMER5 36 48 #define SRST_P_JDBCK_DAP 37 49 #define SRST_JDBCK_DAP 38 50 #define SRST_P_WDT_NS 39 51 #define SRST_T_WDT_NS 40 52 #define SRST_H_TRNG_NS 41 53 #define SRST_P_UART0 42 54 #define SRST_S_UART0 43 55 #define SRST_PKA_CRYPTO 44 56 #define SRST_A_CRYPTO 45 57 #define SRST_H_CRYPTO 46 58 #define SRST_P_DMA2DDR 47 59 #define SRST_A_DMA2DDR 48 60 #define SRST_P_PWM0 49 61 #define SRST_PWM0 50 62 #define SRST_P_PWM1 51 63 #define SRST_PWM1 52 64 #define SRST_P_SCR 53 65 #define SRST_A_DCF 54 66 #define SRST_P_INTMUX 55 67 #define SRST_A_VPU_BIU 56 68 #define SRST_H_VPU_BIU 57 69 #define SRST_P_VPU_BIU 58 70 #define SRST_A_VPU 59 71 #define SRST_H_VPU 60 72 #define SRST_P_CRU_PCIE 61 73 #define SRST_P_VPU_GRF 62 74 #define SRST_H_SFC 63 75 #define SRST_S_SFC 64 76 #define SRST_C_EMMC 65 77 #define SRST_H_EMMC 66 78 #define SRST_A_EMMC 67 79 #define SRST_B_EMMC 68 80 #define SRST_T_EMMC 69 81 #define SRST_P_GPIO1 70 82 #define SRST_DB_GPIO1 71 83 #define SRST_A_VPU_L_BIU 72 84 #define SRST_P_VPU_IOC 73 85 #define SRST_H_SAI_I2S0 74 86 #define SRST_M_SAI_I2S0 75 87 #define SRST_H_SAI_I2S2 76 88 #define SRST_M_SAI_I2S2 77 89 #define SRST_P_ACODEC 78 90 #define SRST_P_GPIO3 79 91 #define SRST_DB_GPIO3 80 92 #define SRST_P_SPI1 81 93 #define SRST_SPI1 82 94 #define SRST_P_UART2 83 95 #define SRST_S_UART2 84 96 #define SRST_P_UART5 85 97 #define SRST_S_UART5 86 98 #define SRST_P_UART6 87 99 #define SRST_S_UART6 88 100 #define SRST_P_UART7 89 101 #define SRST_S_UART7 90 102 #define SRST_P_I2C3 91 103 #define SRST_I2C3 92 104 #define SRST_P_I2C5 93 105 #define SRST_I2C5 94 106 #define SRST_P_I2C6 95 107 #define SRST_I2C6 96 108 #define SRST_A_MAC 97 109 #define SRST_P_PCIE 98 110 #define SRST_PCIE_PIPE_PHY 99 111 #define SRST_PCIE_POWER_UP 100 112 #define SRST_P_PCIE_PHY 101 113 #define SRST_P_PIPE_GRF 102 114 #define SRST_H_SDIO0 103 115 #define SRST_H_SDIO1 104 116 #define SRST_TS_0 105 117 #define SRST_TS_1 106 118 #define SRST_P_CAN2 107 119 #define SRST_CAN2 108 120 #define SRST_P_CAN3 109 121 #define SRST_CAN3 110 122 #define SRST_P_SARADC 111 123 #define SRST_SARADC 112 124 #define SRST_SARADC_PHY 113 125 #define SRST_P_TSADC 114 126 #define SRST_TSADC 115 127 #define SRST_A_USB3OTG 116 128 #define SRST_A_GPU_BIU 117 129 #define SRST_P_GPU_BIU 118 130 #define SRST_A_GPU 119 131 #define SRST_REF_PVTPLL_GPU 120 132 #define SRST_H_RKVENC_BIU 121 133 #define SRST_A_RKVENC_BIU 122 134 #define SRST_P_RKVENC_BIU 123 135 #define SRST_H_RKVENC 124 136 #define SRST_A_RKVENC 125 137 #define SRST_CORE_RKVENC 126 138 #define SRST_H_SAI_I2S1 127 139 #define SRST_M_SAI_I2S1 128 140 #define SRST_P_I2C1 129 141 #define SRST_I2C1 130 142 #define SRST_P_I2C0 131 143 #define SRST_I2C0 132 144 #define SRST_P_SPI0 133 145 #define SRST_SPI0 134 146 #define SRST_P_GPIO4 135 147 #define SRST_DB_GPIO4 136 148 #define SRST_P_RKVENC_IOC 137 149 #define SRST_H_SPDIF 138 150 #define SRST_M_SPDIF 139 151 #define SRST_H_PDM 140 152 #define SRST_M_PDM 141 153 #define SRST_P_UART1 142 154 #define SRST_S_UART1 143 155 #define SRST_P_UART3 144 156 #define SRST_S_UART3 145 157 #define SRST_P_RKVENC_GRF 146 158 #define SRST_P_CAN0 147 159 #define SRST_CAN0 148 160 #define SRST_P_CAN1 149 161 #define SRST_CAN1 150 162 #define SRST_A_VO_BIU 151 163 #define SRST_H_VO_BIU 152 164 #define SRST_P_VO_BIU 153 165 #define SRST_H_RGA2E 154 166 #define SRST_A_RGA2E 155 167 #define SRST_CORE_RGA2E 156 168 #define SRST_H_VDPP 157 169 #define SRST_A_VDPP 158 170 #define SRST_CORE_VDPP 159 171 #define SRST_P_VO_GRF 160 172 #define SRST_P_CRU 161 173 #define SRST_A_VOP_BIU 162 174 #define SRST_H_VOP 163 175 #define SRST_D_VOP0 164 176 #define SRST_D_VOP1 165 177 #define SRST_A_VOP 166 178 #define SRST_P_HDMI 167 179 #define SRST_HDMI 168 180 #define SRST_P_HDMIPHY 169 181 #define SRST_H_HDCP_KEY 170 182 #define SRST_A_HDCP 171 183 #define SRST_H_HDCP 172 184 #define SRST_P_HDCP 173 185 #define SRST_H_CVBS 174 186 #define SRST_D_CVBS_VOP 175 187 #define SRST_D_4X_CVBS_VOP 176 188 #define SRST_A_JPEG_DECODER 177 189 #define SRST_H_JPEG_DECODER 178 190 #define SRST_A_VO_L_BIU 179 191 #define SRST_A_MAC_VO 180 192 #define SRST_A_JPEG_BIU 181 193 #define SRST_H_SAI_I2S3 182 194 #define SRST_M_SAI_I2S3 183 195 #define SRST_MACPHY 184 196 #define SRST_P_VCDCPHY 185 197 #define SRST_P_GPIO2 186 198 #define SRST_DB_GPIO2 187 199 #define SRST_P_VO_IOC 188 200 #define SRST_H_SDMMC0 189 201 #define SRST_P_OTPC_NS 190 202 #define SRST_SBPI_OTPC_NS 191 203 #define SRST_USER_OTPC_NS 192 204 #define SRST_HDMIHDP0 193 205 #define SRST_H_USBHOST 194 206 #define SRST_H_USBHOST_ARB 195 207 #define SRST_HOST_UTMI 196 208 #define SRST_P_UART4 197 209 #define SRST_S_UART4 198 210 #define SRST_P_I2C4 199 211 #define SRST_I2C4 200 212 #define SRST_P_I2C7 201 213 #define SRST_I2C7 202 214 #define SRST_P_USBPHY 203 215 #define SRST_USBPHY_POR 204 216 #define SRST_USBPHY_OTG 205 217 #define SRST_USBPHY_HOST 206 218 #define SRST_P_DDRPHY_CRU 207 219 #define SRST_H_RKVDEC_BIU 208 220 #define SRST_A_RKVDEC_BIU 209 221 #define SRST_A_RKVDEC 210 222 #define SRST_H_RKVDEC 211 223 #define SRST_HEVC_CA_RKVDEC 212 224 #define SRST_REF_PVTPLL_RKVDEC 213 225 #define SRST_P_DDR_BIU 214 226 #define SRST_P_DDRC 215 227 #define SRST_P_DDRMON 216 228 #define SRST_TIMER_DDRMON 217 229 #define SRST_P_MSCH_BIU 218 230 #define SRST_P_DDR_GRF 219 231 #define SRST_P_DDR_HWLP 220 232 #define SRST_P_DDRPHY 221 233 #define SRST_MSCH_BIU 222 234 #define SRST_A_DDR_UPCTL 223 235 #define SRST_DDR_UPCTL 224 236 #define SRST_DDRMON 225 237 #define SRST_A_DDR_SCRAMBLE 226 238 #define SRST_A_SPLIT 227 239 #define SRST_DDR_PHY 228 240 241 #endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H 242