1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved. */ 3 4 #ifndef DT_BINDINGS_RESET_NVIDIA_TEGRA264_H 5 #define DT_BINDINGS_RESET_NVIDIA_TEGRA264_H 6 7 #define TEGRA264_RESET_APE_TKE 1 8 #define TEGRA264_RESET_CEC 2 9 #define TEGRA264_RESET_ADSP_ALL 3 10 #define TEGRA264_RESET_RCE_ALL 4 11 #define TEGRA264_RESET_UFSHC 5 12 #define TEGRA264_RESET_UFSHC_AXI_M 6 13 #define TEGRA264_RESET_UFSHC_LP_SEQ 7 14 #define TEGRA264_RESET_DPAUX 8 15 #define TEGRA264_RESET_EQOS_PCS 9 16 #define TEGRA264_RESET_HWPM 10 17 #define TEGRA264_RESET_I2C1 11 18 #define TEGRA264_RESET_I2C2 12 19 #define TEGRA264_RESET_I2C3 13 20 #define TEGRA264_RESET_I2C4 14 21 #define TEGRA264_RESET_I2C6 15 22 #define TEGRA264_RESET_I2C7 16 23 #define TEGRA264_RESET_I2C8 17 24 #define TEGRA264_RESET_I2C9 18 25 #define TEGRA264_RESET_ISP 19 26 #define TEGRA264_RESET_LA 20 27 #define TEGRA264_RESET_NVCSI 21 28 #define TEGRA264_RESET_EQOS_MAC 22 29 #define TEGRA264_RESET_PWM10 23 30 #define TEGRA264_RESET_PWM2 24 31 #define TEGRA264_RESET_PWM3 25 32 #define TEGRA264_RESET_PWM4 26 33 #define TEGRA264_RESET_PWM5 27 34 #define TEGRA264_RESET_PWM9 28 35 #define TEGRA264_RESET_QSPI0 29 36 #define TEGRA264_RESET_HDA 30 37 #define TEGRA264_RESET_HDACODEC 31 38 #define TEGRA264_RESET_I2C0 32 39 #define TEGRA264_RESET_I2C10 33 40 #define TEGRA264_RESET_SDMMC1 34 41 #define TEGRA264_RESET_MIPI_CAL 35 42 #define TEGRA264_RESET_SPI1 36 43 #define TEGRA264_RESET_SPI2 37 44 #define TEGRA264_RESET_SPI3 38 45 #define TEGRA264_RESET_SPI4 39 46 #define TEGRA264_RESET_SPI5 40 47 #define TEGRA264_RESET_SPI7 41 48 #define TEGRA264_RESET_SPI8 42 49 #define TEGRA264_RESET_SPI9 43 50 #define TEGRA264_RESET_TACH0 44 51 #define TEGRA264_RESET_TSEC 45 52 #define TEGRA264_RESET_VI 46 53 #define TEGRA264_RESET_VI1 47 54 #define TEGRA264_RESET_PVA0_ALL 48 55 #define TEGRA264_RESET_VIC 49 56 #define TEGRA264_RESET_MPHY_CLK_CTL 50 57 #define TEGRA264_RESET_MPHY_L0_RX 51 58 #define TEGRA264_RESET_MPHY_L0_TX 52 59 #define TEGRA264_RESET_MPHY_L1_RX 53 60 #define TEGRA264_RESET_MPHY_L1_TX 54 61 #define TEGRA264_RESET_ISP1 55 62 #define TEGRA264_RESET_I2C11 56 63 #define TEGRA264_RESET_I2C12 57 64 #define TEGRA264_RESET_I2C14 58 65 #define TEGRA264_RESET_I2C15 59 66 #define TEGRA264_RESET_I2C16 60 67 #define TEGRA264_RESET_EQOS_MACSEC 61 68 #define TEGRA264_RESET_MGBE0_PCS 62 69 #define TEGRA264_RESET_MGBE0_MAC 63 70 #define TEGRA264_RESET_MGBE0_MACSEC 64 71 #define TEGRA264_RESET_MGBE1_PCS 65 72 #define TEGRA264_RESET_MGBE1_MAC 66 73 #define TEGRA264_RESET_MGBE1_MACSEC 67 74 #define TEGRA264_RESET_MGBE2_PCS 68 75 #define TEGRA264_RESET_MGBE2_MAC 69 76 #define TEGRA264_RESET_MGBE2_MACSEC 70 77 #define TEGRA264_RESET_MGBE3_PCS 71 78 #define TEGRA264_RESET_MGBE3_MAC 72 79 #define TEGRA264_RESET_MGBE3_MACSEC 73 80 #define TEGRA264_RESET_ADSP_CORE0 74 81 #define TEGRA264_RESET_ADSP_CORE1 75 82 #define TEGRA264_RESET_APE 76 83 #define TEGRA264_RESET_XUSB1_PADCTL 77 84 #define TEGRA264_RESET_AON_CPU_ALL 78 85 #define TEGRA264_RESET_AON_HSP 79 86 #define TEGRA264_RESET_UART4 80 87 #define TEGRA264_RESET_UART5 81 88 #define TEGRA264_RESET_UART9 82 89 #define TEGRA264_RESET_UART10 83 90 #define TEGRA264_RESET_UART8 84 91 92 #endif /* DT_BINDINGS_RESET_NVIDIA_TEGRA264_H */ 93