1*82d58440SIrving-CH Lin /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*82d58440SIrving-CH Lin /* 3*82d58440SIrving-CH Lin * Copyright (c) 2025 MediaTek Inc. 4*82d58440SIrving-CH Lin * Author: Qiqi Wang <qiqi.wang@mediatek.com> 5*82d58440SIrving-CH Lin */ 6*82d58440SIrving-CH Lin 7*82d58440SIrving-CH Lin #ifndef _DT_BINDINGS_POWER_MT8189_POWER_H 8*82d58440SIrving-CH Lin #define _DT_BINDINGS_POWER_MT8189_POWER_H 9*82d58440SIrving-CH Lin 10*82d58440SIrving-CH Lin /* SPM */ 11*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_CONN 0 12*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_AUDIO 1 13*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT 2 14*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_ADSP_INFRA 3 15*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_ADSP_AO 4 16*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_MM_INFRA 5 17*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_ISP_IMG1 6 18*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_ISP_IMG2 7 19*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_ISP_IPE 8 20*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_VDE0 9 21*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_VEN0 10 22*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_CAM_MAIN 11 23*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_CAM_SUBA 12 24*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_CAM_SUBB 13 25*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_MDP0 14 26*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_DISP 15 27*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_DP_TX 16 28*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_CSI_RX 17 29*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_SSUSB 18 30*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_MFG0 19 31*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_MFG1 20 32*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_MFG2 21 33*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_MFG3 22 34*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_EDP_TX_DORMANT 23 35*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_PCIE 24 36*82d58440SIrving-CH Lin #define MT8189_POWER_DOMAIN_PCIE_PHY 25 37*82d58440SIrving-CH Lin 38*82d58440SIrving-CH Lin #endif /* _DT_BINDINGS_POWER_MT8189_POWER_H */ 39