1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2025 MediaTek Inc. 4 * Author: Qiqi Wang <qiqi.wang@mediatek.com> 5 */ 6 7 #ifndef _DT_BINDINGS_POWER_MT8189_POWER_H 8 #define _DT_BINDINGS_POWER_MT8189_POWER_H 9 10 /* SPM */ 11 #define MT8189_POWER_DOMAIN_CONN 0 12 #define MT8189_POWER_DOMAIN_AUDIO 1 13 #define MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT 2 14 #define MT8189_POWER_DOMAIN_ADSP_INFRA 3 15 #define MT8189_POWER_DOMAIN_ADSP_AO 4 16 #define MT8189_POWER_DOMAIN_MM_INFRA 5 17 #define MT8189_POWER_DOMAIN_ISP_IMG1 6 18 #define MT8189_POWER_DOMAIN_ISP_IMG2 7 19 #define MT8189_POWER_DOMAIN_ISP_IPE 8 20 #define MT8189_POWER_DOMAIN_VDE0 9 21 #define MT8189_POWER_DOMAIN_VEN0 10 22 #define MT8189_POWER_DOMAIN_CAM_MAIN 11 23 #define MT8189_POWER_DOMAIN_CAM_SUBA 12 24 #define MT8189_POWER_DOMAIN_CAM_SUBB 13 25 #define MT8189_POWER_DOMAIN_MDP0 14 26 #define MT8189_POWER_DOMAIN_DISP 15 27 #define MT8189_POWER_DOMAIN_DP_TX 16 28 #define MT8189_POWER_DOMAIN_CSI_RX 17 29 #define MT8189_POWER_DOMAIN_SSUSB 18 30 #define MT8189_POWER_DOMAIN_MFG0 19 31 #define MT8189_POWER_DOMAIN_MFG1 20 32 #define MT8189_POWER_DOMAIN_MFG2 21 33 #define MT8189_POWER_DOMAIN_MFG3 22 34 #define MT8189_POWER_DOMAIN_EDP_TX_DORMANT 23 35 #define MT8189_POWER_DOMAIN_PCIE 24 36 #define MT8189_POWER_DOMAIN_PCIE_PHY 25 37 38 #endif /* _DT_BINDINGS_POWER_MT8189_POWER_H */ 39