1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Copyright (c) 2025 Collabora Ltd 4 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 5 */ 6 7 #ifndef _DT_BINDINGS_POWER_MT8196_POWER_H 8 #define _DT_BINDINGS_POWER_MT8196_POWER_H 9 10 /* SCPSYS Secure Power Manager - Direct Control */ 11 #define MT8196_POWER_DOMAIN_MD 0 12 #define MT8196_POWER_DOMAIN_CONN 1 13 #define MT8196_POWER_DOMAIN_SSUSB_P0 2 14 #define MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0 3 15 #define MT8196_POWER_DOMAIN_SSUSB_P1 4 16 #define MT8196_POWER_DOMAIN_SSUSB_P23 5 17 #define MT8196_POWER_DOMAIN_SSUSB_PHY_P2 6 18 #define MT8196_POWER_DOMAIN_PEXTP_MAC0 7 19 #define MT8196_POWER_DOMAIN_PEXTP_MAC1 8 20 #define MT8196_POWER_DOMAIN_PEXTP_MAC2 9 21 #define MT8196_POWER_DOMAIN_PEXTP_PHY0 10 22 #define MT8196_POWER_DOMAIN_PEXTP_PHY1 11 23 #define MT8196_POWER_DOMAIN_PEXTP_PHY2 12 24 #define MT8196_POWER_DOMAIN_AUDIO 13 25 #define MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT 14 26 #define MT8196_POWER_DOMAIN_ADSP_INFRA 15 27 #define MT8196_POWER_DOMAIN_ADSP_AO 16 28 29 /* SCPSYS Secure Power Manager - HW Voter */ 30 #define MT8196_POWER_DOMAIN_MM_PROC_DORMANT 0 31 #define MT8196_POWER_DOMAIN_SSR 1 32 33 /* HFRPSYS MultiMedia Power Control (MMPC) - HW Voter */ 34 #define MT8196_POWER_DOMAIN_VDE0 0 35 #define MT8196_POWER_DOMAIN_VDE1 1 36 #define MT8196_POWER_DOMAIN_VDE_VCORE0 2 37 #define MT8196_POWER_DOMAIN_VEN0 3 38 #define MT8196_POWER_DOMAIN_VEN1 4 39 #define MT8196_POWER_DOMAIN_VEN2 5 40 #define MT8196_POWER_DOMAIN_DISP_VCORE 6 41 #define MT8196_POWER_DOMAIN_DIS0_DORMANT 7 42 #define MT8196_POWER_DOMAIN_DIS1_DORMANT 8 43 #define MT8196_POWER_DOMAIN_OVL0_DORMANT 9 44 #define MT8196_POWER_DOMAIN_OVL1_DORMANT 10 45 #define MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT 11 46 #define MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT 12 47 #define MT8196_POWER_DOMAIN_MML0_SHUTDOWN 13 48 #define MT8196_POWER_DOMAIN_MML1_SHUTDOWN 14 49 #define MT8196_POWER_DOMAIN_MM_INFRA0 15 50 #define MT8196_POWER_DOMAIN_MM_INFRA1 16 51 #define MT8196_POWER_DOMAIN_MM_INFRA_AO 17 52 #define MT8196_POWER_DOMAIN_CSI_BS_RX 18 53 #define MT8196_POWER_DOMAIN_CSI_LS_RX 19 54 #define MT8196_POWER_DOMAIN_DSI_PHY0 20 55 #define MT8196_POWER_DOMAIN_DSI_PHY1 21 56 #define MT8196_POWER_DOMAIN_DSI_PHY2 22 57 58 #endif /* _DT_BINDINGS_POWER_MT8196_POWER_H */ 59