1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ 3 4 #ifndef DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H 5 #define DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H 6 7 #define TEGRA264_SID(x) ((x) << 8) 8 9 /* 10 * SMMU stream IDs 11 */ 12 13 #define TEGRA264_SID_AON TEGRA264_SID(0x01) 14 #define TEGRA264_SID_APE TEGRA264_SID(0x02) 15 #define TEGRA264_SID_ETR TEGRA264_SID(0x03) 16 #define TEGRA264_SID_BPMP TEGRA264_SID(0x04) 17 #define TEGRA264_SID_DCE TEGRA264_SID(0x05) 18 #define TEGRA264_SID_EQOS TEGRA264_SID(0x06) 19 #define TEGRA264_SID_GPCDMA TEGRA264_SID(0x08) 20 #define TEGRA264_SID_DISP TEGRA264_SID(0x09) 21 #define TEGRA264_SID_HDA TEGRA264_SID(0x0a) 22 #define TEGRA264_SID_HOST1X TEGRA264_SID(0x0b) 23 #define TEGRA264_SID_ISP0 TEGRA264_SID(0x0c) 24 #define TEGRA264_SID_ISP1 TEGRA264_SID(0x0d) 25 #define TEGRA264_SID_PMA0 TEGRA264_SID(0x0e) 26 #define TEGRA264_SID_FSI0 TEGRA264_SID(0x0f) 27 #define TEGRA264_SID_FSI1 TEGRA264_SID(0x10) 28 #define TEGRA264_SID_PVA TEGRA264_SID(0x11) 29 #define TEGRA264_SID_SDMMC0 TEGRA264_SID(0x12) 30 #define TEGRA264_SID_MGBE0 TEGRA264_SID(0x13) 31 #define TEGRA264_SID_MGBE1 TEGRA264_SID(0x14) 32 #define TEGRA264_SID_MGBE2 TEGRA264_SID(0x15) 33 #define TEGRA264_SID_MGBE3 TEGRA264_SID(0x16) 34 #define TEGRA264_SID_MSSSEQ TEGRA264_SID(0x17) 35 #define TEGRA264_SID_SE TEGRA264_SID(0x18) 36 #define TEGRA264_SID_SEU1 TEGRA264_SID(0x19) 37 #define TEGRA264_SID_SEU2 TEGRA264_SID(0x1a) 38 #define TEGRA264_SID_SEU3 TEGRA264_SID(0x1b) 39 #define TEGRA264_SID_PSC TEGRA264_SID(0x1c) 40 #define TEGRA264_SID_OESP TEGRA264_SID(0x23) 41 #define TEGRA264_SID_SB TEGRA264_SID(0x24) 42 #define TEGRA264_SID_XSPI0 TEGRA264_SID(0x25) 43 #define TEGRA264_SID_TSEC TEGRA264_SID(0x29) 44 #define TEGRA264_SID_UFS TEGRA264_SID(0x2a) 45 #define TEGRA264_SID_RCE TEGRA264_SID(0x2b) 46 #define TEGRA264_SID_RCE1 TEGRA264_SID(0x2c) 47 #define TEGRA264_SID_VI TEGRA264_SID(0x2e) 48 #define TEGRA264_SID_VI1 TEGRA264_SID(0x2f) 49 #define TEGRA264_SID_VIC TEGRA264_SID(0x30) 50 #define TEGRA264_SID_XUSB_DEV TEGRA264_SID(0x32) 51 #define TEGRA264_SID_XUSB_DEV1 TEGRA264_SID(0x33) 52 #define TEGRA264_SID_XUSB_DEV2 TEGRA264_SID(0x34) 53 #define TEGRA264_SID_XUSB_DEV3 TEGRA264_SID(0x35) 54 #define TEGRA264_SID_XUSB_DEV4 TEGRA264_SID(0x36) 55 #define TEGRA264_SID_XUSB_DEV5 TEGRA264_SID(0x37) 56 57 /* 58 * memory client IDs 59 */ 60 61 /* PTW read client mapped to SOC SMMU0 */ 62 #define TEGRA264_MEMORY_CLIENT_PTCR 0x00 63 /* HOST1X read client */ 64 #define TEGRA264_MEMORY_CLIENT_HOST1XR 0x16 65 #define TEGRA264_MEMORY_CLIENT_MPCORER 0x27 66 /* Platform security (PSC) Read clients */ 67 #define TEGRA264_MEMORY_CLIENT_PSCR 0x33 68 /* PSC Write clients */ 69 #define TEGRA264_MEMORY_CLIENT_PSCW 0x34 70 /* ISP0 Read client */ 71 #define TEGRA264_MEMORY_CLIENT_ISP0R 0x37 72 #define TEGRA264_MEMORY_CLIENT_MPCOREW 0x39 73 /* ISP0 Write client */ 74 #define TEGRA264_MEMORY_CLIENT_ISP0W 0x44 75 /* ISP1 Write client */ 76 #define TEGRA264_MEMORY_CLIENT_ISP1W 0x45 77 /* ISP FALCON Read client */ 78 #define TEGRA264_MEMORY_CLIENT_ISPFALCONR 0x47 79 /* ISP FALCON Write client */ 80 #define TEGRA264_MEMORY_CLIENT_ISPFALCONW 0x4f 81 /* MGBE2 Read mccif */ 82 #define TEGRA264_MEMORY_CLIENT_MGBE2R 0x5c 83 #define TEGRA264_MEMORY_CLIENT_OFAR2MC 0x5d 84 #define TEGRA264_MEMORY_CLIENT_OFAW2MC 0x5e 85 /* MGBE2 Write mccif */ 86 #define TEGRA264_MEMORY_CLIENT_MGBE2W 0x5f 87 /* MGBE3 Read mccif */ 88 #define TEGRA264_MEMORY_CLIENT_MGBE3R 0x61 89 /* MGBE3 Write mccif */ 90 #define TEGRA264_MEMORY_CLIENT_MGBE3W 0x65 91 /* SEU1 Memory Read Client */ 92 #define TEGRA264_MEMORY_CLIENT_SEU1RD 0x68 93 /* SEU1 Memory Write Client */ 94 #define TEGRA264_MEMORY_CLIENT_SEU1WR 0x69 95 /* VIC read client */ 96 #define TEGRA264_MEMORY_CLIENT_VICR 0x6c 97 /* VIC Write client */ 98 #define TEGRA264_MEMORY_CLIENT_VICW 0x6d 99 /* VI R5 Write client */ 100 #define TEGRA264_MEMORY_CLIENT_VIW 0x72 101 /* QSPI Read Client */ 102 #define TEGRA264_MEMORY_CLIENT_XSPI0R 0x75 103 /* QSPI Write Client */ 104 #define TEGRA264_MEMORY_CLIENT_XSPI0W 0x76 105 #define TEGRA264_MEMORY_CLIENT_NVDECSRD2MC 0x78 106 #define TEGRA264_MEMORY_CLIENT_NVDECSWR2MC 0x79 107 /* Audio processor(APE) Read client */ 108 #define TEGRA264_MEMORY_CLIENT_APER 0x7a 109 /* Audio processor(APE) Write client */ 110 #define TEGRA264_MEMORY_CLIENT_APEW 0x7b 111 /* SEU0 read client */ 112 #define TEGRA264_MEMORY_CLIENT_SER 0x80 113 /* SEU0 write client */ 114 #define TEGRA264_MEMORY_CLIENT_SEW 0x81 115 /* AXI AP and DFD/Coresight1-AUX0/1 Read clients both share the same interface on MSS */ 116 #define TEGRA264_MEMORY_CLIENT_AXIAPR 0x82 117 /* AXI AP and DFD/Coresight1-AUX0/1 Write clients both share the same interface on MSS */ 118 #define TEGRA264_MEMORY_CLIENT_AXIAPW 0x83 119 /* ETR or DFD/Coresight0 Read Client */ 120 #define TEGRA264_MEMORY_CLIENT_ETRR 0x84 121 /* ETR or DFD/Coresight0 Write Client */ 122 #define TEGRA264_MEMORY_CLIENT_ETRW 0x85 123 /* Security(tsec) Read client */ 124 #define TEGRA264_MEMORY_CLIENT_TSECR 0x86 125 /* Security(tsec) Write client */ 126 #define TEGRA264_MEMORY_CLIENT_TSECW 0x87 127 /* BPMP read client */ 128 #define TEGRA264_MEMORY_CLIENT_BPMPR 0x93 129 /* BPMP write client */ 130 #define TEGRA264_MEMORY_CLIENT_BPMPW 0x94 131 /* AON Read Client */ 132 #define TEGRA264_MEMORY_CLIENT_AONR 0x97 133 /* AON write client */ 134 #define TEGRA264_MEMORY_CLIENT_AONW 0x98 135 /* GPCDMA debug Read client */ 136 #define TEGRA264_MEMORY_CLIENT_GPCDMAR 0x99 137 /* GPCDMA debug Write client */ 138 #define TEGRA264_MEMORY_CLIENT_GPCDMAW 0x9a 139 /* Audio DMA Read client */ 140 #define TEGRA264_MEMORY_CLIENT_APEDMAR 0x9f 141 /* Audio DMA Write client */ 142 #define TEGRA264_MEMORY_CLIENT_APEDMAW 0xa0 143 /* mss internal memqual MIU0 reads */ 144 #define TEGRA264_MEMORY_CLIENT_MIU0R 0xa6 145 /* mss internal memqual MIU0 writes */ 146 #define TEGRA264_MEMORY_CLIENT_MIU0W 0xa7 147 /* mss internal memqual MIU1 reads */ 148 #define TEGRA264_MEMORY_CLIENT_MIU1R 0xa8 149 /* mss internal memqual MIU1 writes */ 150 #define TEGRA264_MEMORY_CLIENT_MIU1W 0xa9 151 /* mss internal memqual MIU2 reads */ 152 #define TEGRA264_MEMORY_CLIENT_MIU2R 0xae 153 /* mss internal memqual MIU2 writes */ 154 #define TEGRA264_MEMORY_CLIENT_MIU2W 0xaf 155 /* mss internal memqual MIU3 reads */ 156 #define TEGRA264_MEMORY_CLIENT_MIU3R 0xb0 157 /* mss internal memqual MIU3 writes */ 158 #define TEGRA264_MEMORY_CLIENT_MIU3W 0xb1 159 /* mss internal memqual MIU4 reads */ 160 #define TEGRA264_MEMORY_CLIENT_MIU4R 0xb2 161 /* mss internal memqual MIU4 writes */ 162 #define TEGRA264_MEMORY_CLIENT_MIU4W 0xb3 163 #define TEGRA264_MEMORY_CLIENT_GPUR02MC 0xb6 164 #define TEGRA264_MEMORY_CLIENT_GPUW02MC 0xb7 165 /* VI Falcon Read client */ 166 #define TEGRA264_MEMORY_CLIENT_VIFALCONR 0xbc 167 /* VI Falcon Write client */ 168 #define TEGRA264_MEMORY_CLIENT_VIFALCONW 0xbd 169 /* Read Client of RCE */ 170 #define TEGRA264_MEMORY_CLIENT_RCER 0xd2 171 /* Write client of RCE */ 172 #define TEGRA264_MEMORY_CLIENT_RCEW 0xd3 173 #define TEGRA264_MEMORY_CLIENT_NVENC1SRD2MC 0xd6 174 #define TEGRA264_MEMORY_CLIENT_NVENC1SWR2MC 0xd7 175 /* PCIE0/MSI Write clients */ 176 #define TEGRA264_MEMORY_CLIENT_PCIE0W 0xd9 177 /* PCIE1/RPX4 Read clients */ 178 #define TEGRA264_MEMORY_CLIENT_PCIE1R 0xda 179 /* PCIE1/RPX4 Write clients */ 180 #define TEGRA264_MEMORY_CLIENT_PCIE1W 0xdb 181 /* PCIE2/DMX4 Read clients */ 182 #define TEGRA264_MEMORY_CLIENT_PCIE2AR 0xdc 183 /* PCIE2/DMX4 Write clients */ 184 #define TEGRA264_MEMORY_CLIENT_PCIE2AW 0xdd 185 /* PCIE3/RPX4 Read clients */ 186 #define TEGRA264_MEMORY_CLIENT_PCIE3R 0xde 187 /* PCIE3/RPX4 Write clients */ 188 #define TEGRA264_MEMORY_CLIENT_PCIE3W 0xdf 189 /* PCIE4/DMX8 Read clients */ 190 #define TEGRA264_MEMORY_CLIENT_PCIE4R 0xe0 191 /* PCIE4/DMX8 Write clients */ 192 #define TEGRA264_MEMORY_CLIENT_PCIE4W 0xe1 193 /* PCIE5/DMX4 Read clients */ 194 #define TEGRA264_MEMORY_CLIENT_PCIE5R 0xe2 195 /* PCIE5/DMX4 Write clients */ 196 #define TEGRA264_MEMORY_CLIENT_PCIE5W 0xe3 197 /* mss internal memqual MIU5 reads */ 198 #define TEGRA264_MEMORY_CLIENT_MIU5R 0xfc 199 /* mss internal memqual MIU5 writes */ 200 #define TEGRA264_MEMORY_CLIENT_MIU5W 0xfd 201 /* mss internal memqual MIU6 writes */ 202 #define TEGRA264_MEMORY_CLIENT_MIU6W 0xff 203 #define TEGRA264_MEMORY_CLIENT_RISTR 0x100 204 #define TEGRA264_MEMORY_CLIENT_RISTW 0x101 205 /* OESP (Pluton) Read client */ 206 #define TEGRA264_MEMORY_CLIENT_OESPR 0x102 207 /* OESP (Pluton) Write client */ 208 #define TEGRA264_MEMORY_CLIENT_OESPW 0x103 209 /* mss internal memqual MIU7 writes */ 210 #define TEGRA264_MEMORY_CLIENT_MIU7W 0x105 211 /* mss internal memqual MIU8 reads */ 212 #define TEGRA264_MEMORY_CLIENT_MIU8R 0x106 213 /* mss internal memqual MIU8 writes */ 214 #define TEGRA264_MEMORY_CLIENT_MIU8W 0x107 215 /* mss internal memqual MIU9 reads */ 216 #define TEGRA264_MEMORY_CLIENT_MIU9R 0x108 217 /* mss internal memqual MIU9 writes */ 218 #define TEGRA264_MEMORY_CLIENT_MIU9W 0x109 219 /* HWPM Write Interface */ 220 #define TEGRA264_MEMORY_CLIENT_PMA0AWR 0x122 221 #define TEGRA264_MEMORY_CLIENT_NVJPG1SRD2MC 0x123 222 #define TEGRA264_MEMORY_CLIENT_NVJPG1SWR2MC 0x124 223 /* CTW read client mapped to SMMU0 */ 224 #define TEGRA264_MEMORY_CLIENT_SMMU0CTWR 0x12e 225 /* CMDQV read client mapped to SMMU0 */ 226 #define TEGRA264_MEMORY_CLIENT_SMMU0CMDQVR 0x12f 227 /* CMDQV write client mapped to SMMU0 */ 228 #define TEGRA264_MEMORY_CLIENT_SMMU0CMDQVW 0x130 229 /* EVNTQ write client mapped to SMMU0 */ 230 #define TEGRA264_MEMORY_CLIENT_SMMU0EVNTQW 0x131 231 /* PTW read client mapped to SMMU1 */ 232 #define TEGRA264_MEMORY_CLIENT_SMMU1PTWR 0x132 233 /* CTW read client mapped to SMMU1 */ 234 #define TEGRA264_MEMORY_CLIENT_SMMU1CTWR 0x134 235 /* CMDQV read client mapped to SMMU1 */ 236 #define TEGRA264_MEMORY_CLIENT_SMMU1CMDQVR 0x135 237 /* CMDQV write client mapped to SMMU1 */ 238 #define TEGRA264_MEMORY_CLIENT_SMMU1CMDQVW 0x136 239 /* EVNTQ write client mapped to SMMU1 */ 240 #define TEGRA264_MEMORY_CLIENT_SMMU1EVNTQW 0x137 241 /* PTW read client mapped to SMMU2 */ 242 #define TEGRA264_MEMORY_CLIENT_SMMU2PTWR 0x138 243 /* CTW read client mapped to SMMU2 */ 244 #define TEGRA264_MEMORY_CLIENT_SMMU2CTWR 0x13a 245 /* CMDQV read client mapped to SMMU2 */ 246 #define TEGRA264_MEMORY_CLIENT_SMMU2CMDQVR 0x13b 247 /* CMDQV write client mapped to SMMU2 */ 248 #define TEGRA264_MEMORY_CLIENT_SMMU2CMDQVW 0x13c 249 /* EVNTQ write client mapped to SMMU2 */ 250 #define TEGRA264_MEMORY_CLIENT_SMMU2EVNTQW 0x13d 251 /* CMDQ read client mapped to SMMU0 */ 252 #define TEGRA264_MEMORY_CLIENT_SMMU0CMDQR 0x144 253 /* CMDQ read client mapped to SMMU1 */ 254 #define TEGRA264_MEMORY_CLIENT_SMMU1CMDQR 0x145 255 /* CMDQ read client mapped to SMMU2 */ 256 #define TEGRA264_MEMORY_CLIENT_SMMU2CMDQR 0x146 257 /* Audio processor1(APE1) Read client */ 258 #define TEGRA264_MEMORY_CLIENT_APE1R 0x150 259 /* Audio processor1(APE1) Write client */ 260 #define TEGRA264_MEMORY_CLIENT_APE1W 0x151 261 /* UFS Read client */ 262 #define TEGRA264_MEMORY_CLIENT_UFSR 0x15c 263 /* UFS write client */ 264 #define TEGRA264_MEMORY_CLIENT_UFSW 0x15d 265 /* XUSB HOST Read Client */ 266 #define TEGRA264_MEMORY_CLIENT_XUSB_DEVR 0x166 267 /* XUSB HOST Write Client */ 268 #define TEGRA264_MEMORY_CLIENT_XUSB_DEVW 0x167 269 /* XUSB SS0 Read Client */ 270 #define TEGRA264_MEMORY_CLIENT_XUSB_DEV1R 0x168 271 /* XUSB SS1 Write Client */ 272 #define TEGRA264_MEMORY_CLIENT_XUSB_DEV2W 0x169 273 /* XUSB SS2 Read Client */ 274 #define TEGRA264_MEMORY_CLIENT_XUSB_DEV3R 0x16a 275 /* XUSB SS2 Write Client */ 276 #define TEGRA264_MEMORY_CLIENT_XUSB_DEV3W 0x16b 277 /* XUSB SS3 Read Client */ 278 #define TEGRA264_MEMORY_CLIENT_XUSB_DEV4R 0x16c 279 /* XUSB SS3 Write Client */ 280 #define TEGRA264_MEMORY_CLIENT_XUSB_DEV4W 0x16d 281 /* XUSB DEV Read Client */ 282 #define TEGRA264_MEMORY_CLIENT_XUSB_DEV5R 0x16e 283 /* XUSB DEV Write Client */ 284 #define TEGRA264_MEMORY_CLIENT_XUSB_DEV5W 0x16f 285 /* DCE Read client */ 286 #define TEGRA264_MEMORY_CLIENT_DCER 0x17a 287 /* DCE Write client */ 288 #define TEGRA264_MEMORY_CLIENT_DCEW 0x17b 289 /* HDA Read client */ 290 #define TEGRA264_MEMORY_CLIENT_HDAR 0x17c 291 /* HDA Write client */ 292 #define TEGRA264_MEMORY_CLIENT_HDAW 0x17d 293 /* DISPNISO read client */ 294 #define TEGRA264_MEMORY_CLIENT_DISPNISOR 0x17e 295 /* DISPNISO write client */ 296 #define TEGRA264_MEMORY_CLIENT_DISPNISOW 0x17f 297 /* XUSB SS0 Write Client */ 298 #define TEGRA264_MEMORY_CLIENT_XUSB_DEV1W 0x180 299 /* XUSB SS1 Read Client */ 300 #define TEGRA264_MEMORY_CLIENT_XUSB_DEV2R 0x181 301 /* Disp ISO Read Client */ 302 #define TEGRA264_MEMORY_CLIENT_DISPR 0x182 303 /* MSSSEQ Read Client */ 304 #define TEGRA264_MEMORY_CLIENT_MSSSEQR 0x185 305 /* MSSSEQ Write Client */ 306 #define TEGRA264_MEMORY_CLIENT_MSSSEQW 0x186 307 /* PTW read client mapped to SMMU3 */ 308 #define TEGRA264_MEMORY_CLIENT_SMMU3PTWR 0x18b 309 /* CTW read client mapped to SMMU3 */ 310 #define TEGRA264_MEMORY_CLIENT_SMMU3CTWR 0x18d 311 /* CMDQV read client mapped to SMMU3 */ 312 #define TEGRA264_MEMORY_CLIENT_SMMU3CMDQVR 0x18e 313 /* CMDQV write client mapped to SMMU3 */ 314 #define TEGRA264_MEMORY_CLIENT_SMMU3CMDQVW 0x18f 315 /* EVNTQ write client mapped to SMMU3 */ 316 #define TEGRA264_MEMORY_CLIENT_SMMU3EVNTQW 0x190 317 /* CMDQ read client mapped to SMMU3 */ 318 #define TEGRA264_MEMORY_CLIENT_SMMU3CMDQR 0x191 319 /* PTW read client mapped to SMMU4 */ 320 #define TEGRA264_MEMORY_CLIENT_SMMU4PTWR 0x192 321 /* CTW read client mapped to SMMU4 */ 322 #define TEGRA264_MEMORY_CLIENT_SMMU4CTWR 0x194 323 /* CMDQV read client mapped to SMMU4 */ 324 #define TEGRA264_MEMORY_CLIENT_SMMU4CMDQVR 0x195 325 /* CMDQV write client mapped to SMMU4 */ 326 #define TEGRA264_MEMORY_CLIENT_SMMU4CMDQVW 0x196 327 /* EVNTQ write client mapped to SMMU4 */ 328 #define TEGRA264_MEMORY_CLIENT_SMMU4EVNTQW 0x197 329 /* CMDQ read client mapped to SMMU4 */ 330 #define TEGRA264_MEMORY_CLIENT_SMMU4CMDQR 0x198 331 /* MGBE0 Read mccif */ 332 #define TEGRA264_MEMORY_CLIENT_MGBE0R 0x1a2 333 /* MGBE0 Write mccif */ 334 #define TEGRA264_MEMORY_CLIENT_MGBE0W 0x1a3 335 /* MGBE1 Read mccif */ 336 #define TEGRA264_MEMORY_CLIENT_MGBE1R 0x1a4 337 /* MGBE1 Write mccif */ 338 #define TEGRA264_MEMORY_CLIENT_MGBE1W 0x1a5 339 /* VI1 R5 Write client */ 340 #define TEGRA264_MEMORY_CLIENT_VI1W 0x1a6 341 /* VI Falcon1 Read client */ 342 #define TEGRA264_MEMORY_CLIENT_VIFALCON1R 0x1a7 343 /* VI Falcon1 Write client */ 344 #define TEGRA264_MEMORY_CLIENT_VIFALCON1W 0x1a8 345 /* ISP FALCON1 Read client */ 346 #define TEGRA264_MEMORY_CLIENT_ISPFALCON1R 0x1a9 347 /* ISP FALCON1 Write client */ 348 #define TEGRA264_MEMORY_CLIENT_ISPFALCON1W 0x1aa 349 /* Read Client of RCE1 */ 350 #define TEGRA264_MEMORY_CLIENT_RCE1R 0x1ab 351 /* Write client of RCE1 */ 352 #define TEGRA264_MEMORY_CLIENT_RCE1W 0x1ac 353 /* SEU2 Read client */ 354 #define TEGRA264_MEMORY_CLIENT_SEU2R 0x1ad 355 /* SEU2 Write client */ 356 #define TEGRA264_MEMORY_CLIENT_SEU2W 0x1ae 357 /* SEU3 Read client */ 358 #define TEGRA264_MEMORY_CLIENT_SEU3R 0x1af 359 /* SEU3 Write client */ 360 #define TEGRA264_MEMORY_CLIENT_SEU3W 0x1b0 361 /* PVA0 Falcon Read mccif */ 362 #define TEGRA264_MEMORY_CLIENT_PVA0R 0x1b1 363 /* PVA0 Falcon Write mccif */ 364 #define TEGRA264_MEMORY_CLIENT_PVA0W 0x1b2 365 /* PVA1 Read mccif */ 366 #define TEGRA264_MEMORY_CLIENT_PVA1R 0x1b3 367 /* PVA1 Write mccif */ 368 #define TEGRA264_MEMORY_CLIENT_PVA1W 0x1b4 369 /* PVA2 Read mccif */ 370 #define TEGRA264_MEMORY_CLIENT_PVA2R 0x1b5 371 /* PVA2 Write mccif */ 372 #define TEGRA264_MEMORY_CLIENT_PVA2W 0x1b6 373 /* ISP3 Write client */ 374 #define TEGRA264_MEMORY_CLIENT_ISP3W 0x1b7 375 /* ISP2 Read Client */ 376 #define TEGRA264_MEMORY_CLIENT_ISP2R 0x1b8 377 /* ISP2 Write Client */ 378 #define TEGRA264_MEMORY_CLIENT_ISP2W 0x1b9 379 /* EQOS Read mccif */ 380 #define TEGRA264_MEMORY_CLIENT_EQOSR 0x1bc 381 /* EQOS Write mccif */ 382 #define TEGRA264_MEMORY_CLIENT_EQOSW 0x1bd 383 /* FSI0 Read mccif */ 384 #define TEGRA264_MEMORY_CLIENT_FSI0R 0x1be 385 /* FSI0 Write mccif */ 386 #define TEGRA264_MEMORY_CLIENT_FSI0W 0x1bf 387 /* FSI1 Read mccif */ 388 #define TEGRA264_MEMORY_CLIENT_FSI1R 0x1c0 389 /* FSI1 Write mccif */ 390 #define TEGRA264_MEMORY_CLIENT_FSI1W 0x1c1 391 /* SDMMC0 Read mccif */ 392 #define TEGRA264_MEMORY_CLIENT_SDMMC0R 0x1c2 393 /* SDMMC0 Write mccif */ 394 #define TEGRA264_MEMORY_CLIENT_SDMMC0W 0x1c3 395 /* Strongbox (SB) read client */ 396 #define TEGRA264_MEMORY_CLIENT_SBR 0x1c6 397 /* Strongbox (SB) write client */ 398 #define TEGRA264_MEMORY_CLIENT_SBW 0x1c7 399 #define TEGRA264_MEMORY_CLIENT_HSS_MIU0R 0x1c8 400 #define TEGRA264_MEMORY_CLIENT_HSS_MIU0W 0x1c9 401 #define TEGRA264_MEMORY_CLIENT_HSS_MIU1R 0x1ca 402 #define TEGRA264_MEMORY_CLIENT_HSS_MIU1W 0x1cb 403 #define TEGRA264_MEMORY_CLIENT_HSS_MIU2R 0x1cc 404 #define TEGRA264_MEMORY_CLIENT_HSS_MIU2W 0x1cd 405 #define TEGRA264_MEMORY_CLIENT_HSS_MIU3R 0x1ce 406 #define TEGRA264_MEMORY_CLIENT_HSS_MIU3W 0x1cf 407 #define TEGRA264_MEMORY_CLIENT_HSS_MIU4R 0x1d0 408 #define TEGRA264_MEMORY_CLIENT_HSS_MIU4W 0x1d1 409 #define TEGRA264_MEMORY_CLIENT_HSS_MIU5R 0x1d2 410 #define TEGRA264_MEMORY_CLIENT_HSS_MIU5W 0x1d3 411 #define TEGRA264_MEMORY_CLIENT_HSS_MIU6R 0x1d4 412 #define TEGRA264_MEMORY_CLIENT_HSS_MIU6W 0x1d5 413 #define TEGRA264_MEMORY_CLIENT_HSS_MIU7R 0x1d6 414 #define TEGRA264_MEMORY_CLIENT_HSS_MIU7W 0x1d7 415 #define TEGRA264_MEMORY_CLIENT_GMMUR2MC 0x1d8 416 #define TEGRA264_MEMORY_CLIENT_UCFELAR 0x1d9 417 #define TEGRA264_MEMORY_CLIENT_UCFELAW 0x1da 418 #define TEGRA264_MEMORY_CLIENT_SLCR 0x1db 419 #define TEGRA264_MEMORY_CLIENT_SLCW 0x1dc 420 #define TEGRA264_MEMORY_CLIENT_REMOTER 0x1dd 421 #define TEGRA264_MEMORY_CLIENT_REMOTEW 0x1de 422 423 #endif /* DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H */ 424