xref: /linux/include/dt-bindings/memory/nvidia,tegra238-mc.h (revision 0eaed89c18aeedf0898baf2dbf5ff027c6795152)
1*bf7cf25dSAshish Mhetre /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2*bf7cf25dSAshish Mhetre /* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */
3*bf7cf25dSAshish Mhetre 
4*bf7cf25dSAshish Mhetre #ifndef DT_BINDINGS_MEMORY_TEGRA238_MC_H
5*bf7cf25dSAshish Mhetre #define DT_BINDINGS_MEMORY_TEGRA238_MC_H
6*bf7cf25dSAshish Mhetre 
7*bf7cf25dSAshish Mhetre /* special clients */
8*bf7cf25dSAshish Mhetre #define TEGRA238_SID_INVALID		0x0
9*bf7cf25dSAshish Mhetre #define TEGRA238_SID_PASSTHROUGH	0x7f
10*bf7cf25dSAshish Mhetre 
11*bf7cf25dSAshish Mhetre /* ISO stream IDs */
12*bf7cf25dSAshish Mhetre #define TEGRA238_SID_ISO_NVDISPLAY	0x1
13*bf7cf25dSAshish Mhetre #define TEGRA238_SID_ISO_APE0		0x2
14*bf7cf25dSAshish Mhetre #define TEGRA238_SID_ISO_APE1		0x3
15*bf7cf25dSAshish Mhetre 
16*bf7cf25dSAshish Mhetre /* NISO stream IDs */
17*bf7cf25dSAshish Mhetre #define TEGRA238_SID_AON		0x1
18*bf7cf25dSAshish Mhetre #define TEGRA238_SID_BPMP		0x2
19*bf7cf25dSAshish Mhetre #define TEGRA238_SID_ETR		0x3
20*bf7cf25dSAshish Mhetre #define TEGRA238_SID_FDE		0x4
21*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HC		0x5
22*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HDA		0x6
23*bf7cf25dSAshish Mhetre #define TEGRA238_SID_NVDEC		0x7
24*bf7cf25dSAshish Mhetre #define TEGRA238_SID_NVDISPLAY		0x8
25*bf7cf25dSAshish Mhetre #define TEGRA238_SID_NVENC		0x9
26*bf7cf25dSAshish Mhetre #define TEGRA238_SID_OFA		0xa
27*bf7cf25dSAshish Mhetre #define TEGRA238_SID_PCIE0		0xb
28*bf7cf25dSAshish Mhetre #define TEGRA238_SID_PCIE1		0xc
29*bf7cf25dSAshish Mhetre #define TEGRA238_SID_PCIE2		0xd
30*bf7cf25dSAshish Mhetre #define TEGRA238_SID_PCIE3		0xe
31*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HWMP_PMA		0xf
32*bf7cf25dSAshish Mhetre #define TEGRA238_SID_PSC		0x10
33*bf7cf25dSAshish Mhetre #define TEGRA238_SID_SDMMC1A		0x11
34*bf7cf25dSAshish Mhetre #define TEGRA238_SID_SDMMC4A		0x12
35*bf7cf25dSAshish Mhetre #define TEGRA238_SID_SES_SE0		0x13
36*bf7cf25dSAshish Mhetre #define TEGRA238_SID_SES_SE1		0x14
37*bf7cf25dSAshish Mhetre #define TEGRA238_SID_SES_SE2		0x15
38*bf7cf25dSAshish Mhetre #define TEGRA238_SID_SEU1_SE0		0x16
39*bf7cf25dSAshish Mhetre #define TEGRA238_SID_SEU1_SE1		0x17
40*bf7cf25dSAshish Mhetre #define TEGRA238_SID_SEU1_SE2		0x18
41*bf7cf25dSAshish Mhetre #define TEGRA238_SID_TSEC		0x19
42*bf7cf25dSAshish Mhetre #define TEGRA238_SID_UFSHC		0x1a
43*bf7cf25dSAshish Mhetre #define TEGRA238_SID_VIC		0x1b
44*bf7cf25dSAshish Mhetre #define TEGRA238_SID_XUSB_HOST		0x1c
45*bf7cf25dSAshish Mhetre #define TEGRA238_SID_XUSB_DEV		0x1d
46*bf7cf25dSAshish Mhetre #define TEGRA238_SID_GPCDMA_0		0x1e
47*bf7cf25dSAshish Mhetre #define TEGRA238_SID_SMMU_TEST		0x1f
48*bf7cf25dSAshish Mhetre 
49*bf7cf25dSAshish Mhetre /* Host1x virtualization clients. */
50*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HOST1X_CTX0	0x20
51*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HOST1X_CTX1	0x21
52*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HOST1X_CTX2	0x22
53*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HOST1X_CTX3	0x23
54*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HOST1X_CTX4	0x24
55*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HOST1X_CTX5	0x25
56*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HOST1X_CTX6	0x26
57*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HOST1X_CTX7	0x27
58*bf7cf25dSAshish Mhetre 
59*bf7cf25dSAshish Mhetre #define TEGRA238_SID_XUSB_VF0		0x28
60*bf7cf25dSAshish Mhetre #define TEGRA238_SID_XUSB_VF1		0x29
61*bf7cf25dSAshish Mhetre #define TEGRA238_SID_XUSB_VF2		0x2a
62*bf7cf25dSAshish Mhetre #define TEGRA238_SID_XUSB_VF3		0x2b
63*bf7cf25dSAshish Mhetre 
64*bf7cf25dSAshish Mhetre /* Host1x command buffers */
65*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HC_VM0		0x2c
66*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HC_VM1		0x2d
67*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HC_VM2		0x2e
68*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HC_VM3		0x2f
69*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HC_VM4		0x30
70*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HC_VM5		0x31
71*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HC_VM6		0x32
72*bf7cf25dSAshish Mhetre #define TEGRA238_SID_HC_VM7		0x33
73*bf7cf25dSAshish Mhetre 
74*bf7cf25dSAshish Mhetre #endif
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