1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MAILI_H 7 #define __DT_BINDINGS_INTERCONNECT_QCOM_MAILI_H 8 9 #define MASTER_QSPI_0 0 10 #define MASTER_QUP_2 1 11 #define MASTER_QUP_3 2 12 #define MASTER_QUP_4 3 13 #define MASTER_QUP_5 4 14 #define MASTER_CRYPTO 5 15 #define MASTER_IPA 6 16 #define MASTER_QUP_1 7 17 #define MASTER_SOCCP_PROC 8 18 #define MASTER_QDSS_ETR 9 19 #define MASTER_QDSS_ETR_1 10 20 #define MASTER_SDCC_2 11 21 #define MASTER_SDCC_4 12 22 #define MASTER_UFS_MEM 13 23 #define MASTER_USB3 14 24 #define SLAVE_A1NOC_SNOC 15 25 26 #define MASTER_DDR_EFF_VETO 0 27 #define MASTER_QUP_CORE_0 1 28 #define MASTER_QUP_CORE_1 2 29 #define MASTER_QUP_CORE_2 3 30 #define MASTER_QUP_CORE_3 4 31 #define MASTER_QUP_CORE_4 5 32 #define MASTER_QUP_CORE_5 6 33 #define SLAVE_DDR_EFF_VETO 7 34 #define SLAVE_QUP_CORE_0 8 35 #define SLAVE_QUP_CORE_1 9 36 #define SLAVE_QUP_CORE_2 10 37 #define SLAVE_QUP_CORE_3 11 38 #define SLAVE_QUP_CORE_4 12 39 #define SLAVE_QUP_CORE_5 13 40 41 #define MASTER_GEM_NOC_CNOC 0 42 #define MASTER_GEM_NOC_PCIE_SNOC 1 43 #define SLAVE_AOSS 2 44 #define SLAVE_IPA_CFG 3 45 #define SLAVE_IPC_ROUTER_FENCE 4 46 #define SLAVE_SOCCP 5 47 #define SLAVE_TME_CFG 6 48 #define SLAVE_CNOC_CFG 7 49 #define SLAVE_DDRSS_CFG 8 50 #define SLAVE_IMEM 9 51 #define SLAVE_PCIE_0 10 52 #define SLAVE_PCIE_1 11 53 54 #define MASTER_GIC 0 55 #define MASTER_GPU_TCU 1 56 #define MASTER_SYS_TCU 2 57 #define MASTER_APPSS_PROC 3 58 #define MASTER_GFX3D 4 59 #define MASTER_LPASS_GEM_NOC 5 60 #define MASTER_MSS_PROC 6 61 #define MASTER_MNOC_HF_MEM_NOC 7 62 #define MASTER_MNOC_SF_MEM_NOC 8 63 #define MASTER_COMPUTE_NOC 9 64 #define MASTER_ANOC_PCIE_GEM_NOC 10 65 #define MASTER_QPACE 11 66 #define MASTER_SNOC_SF_MEM_NOC 12 67 #define MASTER_WLAN_Q6 13 68 #define SLAVE_GEM_NOC_CNOC 14 69 #define SLAVE_LLCC 15 70 #define SLAVE_MEM_NOC_PCIE_SNOC 16 71 72 #define MASTER_LPIAON_NOC_LLCLPI_NOC 0 73 #define SLAVE_LPASS_LPI_CC 1 74 #define SLAVE_LLCC_ISLAND 2 75 #define SLAVE_SERVICE_LLCLPI_NOC 3 76 #define SLAVE_SERVICE_LLCLPI_NOC_CHIPCX 4 77 78 #define MASTER_LPIAON_NOC 0 79 #define SLAVE_LPASS_GEM_NOC 1 80 81 #define MASTER_LPASS_LPINOC 0 82 #define SLAVE_LPIAON_NOC_LLCLPI_NOC 1 83 #define SLAVE_LPIAON_NOC_LPASS_AG_NOC 2 84 85 #define MASTER_LPASS_PROC 0 86 #define SLAVE_LPICX_NOC_LPIAON_NOC 1 87 88 #define MASTER_LLCC 0 89 #define MASTER_DDR_RT 1 90 #define SLAVE_EBI1 2 91 #define SLAVE_DDR_RT 3 92 93 #define MASTER_CAMNOC_HF 0 94 #define MASTER_CAMNOC_NRT_ICP_SF 1 95 #define MASTER_CAMNOC_RT_CDM_SF 2 96 #define MASTER_CAMNOC_SF 3 97 #define MASTER_MDP 4 98 #define MASTER_MDSS_DCP 5 99 #define MASTER_CDSP_HCP 6 100 #define MASTER_VIDEO_CV_PROC 7 101 #define MASTER_VIDEO_EVA 8 102 #define MASTER_VIDEO_MVP 9 103 #define MASTER_VIDEO_V_PROC 10 104 #define SLAVE_MNOC_HF_MEM_NOC 11 105 #define SLAVE_MNOC_SF_MEM_NOC 12 106 107 #define MASTER_CDSP_PROC 0 108 #define SLAVE_CDSP_MEM_NOC 1 109 110 #define MASTER_PCIE_ANOC_CFG 0 111 #define MASTER_PCIE_0 1 112 #define MASTER_PCIE_1 2 113 #define SLAVE_ANOC_PCIE_GEM_NOC 3 114 #define SLAVE_SERVICE_PCIE_ANOC 4 115 116 #define MASTER_CFG_CENTER 0 117 #define MASTER_CFG_EAST 1 118 #define MASTER_CFG_MM_HF 2 119 #define MASTER_CFG_MM_SF 3 120 #define MASTER_CFG_NORTH 4 121 #define MASTER_CFG_SOUTH 5 122 #define MASTER_CFG_WEST 6 123 #define SLAVE_AHB2PHY_SOUTH 7 124 #define SLAVE_BOOT_ROM 8 125 #define SLAVE_CAMERA_CFG 9 126 #define SLAVE_CLK_CTL 10 127 #define SLAVE_CRYPTO_CFG 11 128 #define SLAVE_DISPLAY_CFG 12 129 #define SLAVE_EVA_CFG 13 130 #define SLAVE_GFX3D_CFG 14 131 #define SLAVE_I2C 15 132 #define SLAVE_IMEM_CFG 16 133 #define SLAVE_IPC_ROUTER_CFG 17 134 #define SLAVE_IRIS_CFG 18 135 #define SLAVE_CNOC_MSS 19 136 #define SLAVE_PCIE_0_CFG 20 137 #define SLAVE_PCIE_1_CFG 21 138 #define SLAVE_PRNG 22 139 #define SLAVE_QSPI_0 23 140 #define SLAVE_QUP_1 24 141 #define SLAVE_QUP_2 25 142 #define SLAVE_QUP_3 26 143 #define SLAVE_QUP_4 27 144 #define SLAVE_QUP_5 28 145 #define SLAVE_SDCC_2 29 146 #define SLAVE_SDCC_4 30 147 #define SLAVE_TLMM 31 148 #define SLAVE_UFS_MEM_CFG 32 149 #define SLAVE_USB3 33 150 #define SLAVE_VSENSE_CTRL_CFG 34 151 #define SLAVE_PCIE_ANOC_CFG 35 152 #define SLAVE_QDSS_CFG 36 153 #define SLAVE_QDSS_STM 37 154 #define SLAVE_TCSR 38 155 #define SLAVE_TCU 39 156 157 #define MASTER_CNOC_STARDUST 0 158 #define SLAVE_STARDUST_CENTER_CFG 1 159 #define SLAVE_STARDUST_EAST_CFG 2 160 #define SLAVE_STARDUST_MM_HF_CFG 3 161 #define SLAVE_STARDUST_MM_SF_CFG 4 162 #define SLAVE_STARDUST_NORTH_CFG 5 163 #define SLAVE_STARDUST_SOUTH_CFG 6 164 #define SLAVE_STARDUST_WEST_CFG 7 165 166 #define MASTER_A1NOC_SNOC 0 167 #define MASTER_APSS_NOC 1 168 #define MASTER_CNOC_SNOC 2 169 #define SLAVE_SNOC_GEM_NOC_SF 3 170 171 #endif 172