1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_HAWI_H 7 #define __DT_BINDINGS_INTERCONNECT_QCOM_HAWI_H 8 9 #define MASTER_QSPI_0 0 10 #define MASTER_QUP_2 1 11 #define MASTER_QUP_3 2 12 #define MASTER_QUP_4 3 13 #define MASTER_CRYPTO 4 14 #define MASTER_IPA 5 15 #define MASTER_QUP_1 6 16 #define MASTER_SOCCP_PROC 7 17 #define MASTER_QDSS_ETR 8 18 #define MASTER_QDSS_ETR_1 9 19 #define MASTER_SDCC_2 10 20 #define MASTER_SDCC_4 11 21 #define MASTER_UFS_MEM 12 22 #define MASTER_USB3 13 23 #define SLAVE_A1NOC_SNOC 14 24 25 #define MASTER_DDR_EFF_VETO 0 26 #define MASTER_QUP_CORE_0 1 27 #define MASTER_QUP_CORE_1 2 28 #define MASTER_QUP_CORE_2 3 29 #define MASTER_QUP_CORE_3 4 30 #define MASTER_QUP_CORE_4 5 31 #define SLAVE_DDR_EFF_VETO 6 32 #define SLAVE_QUP_CORE_0 7 33 #define SLAVE_QUP_CORE_1 8 34 #define SLAVE_QUP_CORE_2 9 35 #define SLAVE_QUP_CORE_3 10 36 #define SLAVE_QUP_CORE_4 11 37 38 #define MASTER_GEM_NOC_CNOC 0 39 #define MASTER_GEM_NOC_PCIE_SNOC 1 40 #define SLAVE_AOSS 2 41 #define SLAVE_IPA_CFG 3 42 #define SLAVE_IPC_ROUTER_FENCE 4 43 #define SLAVE_SOCCP 5 44 #define SLAVE_TME_CFG 6 45 #define SLAVE_CNOC_CFG 7 46 #define SLAVE_DDRSS_CFG 8 47 #define SLAVE_IMEM 9 48 #define SLAVE_PCIE_0 10 49 #define SLAVE_PCIE_1 11 50 51 #define MASTER_GIC 0 52 #define MASTER_GPU_TCU 1 53 #define MASTER_SYS_TCU 2 54 #define MASTER_APPSS_PROC 3 55 #define MASTER_GFX3D 4 56 #define MASTER_LPASS_GEM_NOC 5 57 #define MASTER_MSS_PROC 6 58 #define MASTER_MNOC_HF_MEM_NOC 7 59 #define MASTER_MNOC_SF_MEM_NOC 8 60 #define MASTER_COMPUTE_NOC 9 61 #define MASTER_ANOC_PCIE_GEM_NOC 10 62 #define MASTER_QPACE 11 63 #define MASTER_SNOC_SF_MEM_NOC 12 64 #define MASTER_WLAN_Q6 13 65 #define SLAVE_GEM_NOC_CNOC 14 66 #define SLAVE_LLCC 15 67 #define SLAVE_MEM_NOC_PCIE_SNOC 16 68 69 #define MASTER_LPIAON_NOC_LLCLPI_NOC 0 70 #define SLAVE_LPASS_LPI_CC 1 71 #define SLAVE_LLCC_ISLAND 2 72 #define SLAVE_SERVICE_LLCLPI_NOC 3 73 #define SLAVE_SERVICE_LLCLPI_NOC_CHIPCX 4 74 75 #define MASTER_LPIAON_NOC 0 76 #define SLAVE_LPASS_GEM_NOC 1 77 78 #define MASTER_LPASS_LPINOC 0 79 #define SLAVE_LPIAON_NOC_LLCLPI_NOC 1 80 #define SLAVE_LPIAON_NOC_LPASS_AG_NOC 2 81 82 #define MASTER_LPASS_PROC 0 83 #define SLAVE_LPICX_NOC_LPIAON_NOC 1 84 85 #define MASTER_LLCC 0 86 #define MASTER_DDR_RT 1 87 #define SLAVE_EBI1 2 88 #define SLAVE_DDR_RT 3 89 90 #define MASTER_CAMNOC_HF 0 91 #define MASTER_CAMNOC_NRT_ICP_SF 1 92 #define MASTER_CAMNOC_RT_CDM_SF 2 93 #define MASTER_CAMNOC_SF 3 94 #define MASTER_MDP 4 95 #define MASTER_MDSS_DCP 5 96 #define MASTER_CDSP_HCP 6 97 #define MASTER_VIDEO_CV_PROC 7 98 #define MASTER_VIDEO_EVA 8 99 #define MASTER_VIDEO_MVP 9 100 #define MASTER_VIDEO_V_PROC 10 101 #define SLAVE_MNOC_HF_MEM_NOC 11 102 #define SLAVE_MNOC_SF_MEM_NOC 12 103 104 #define MASTER_CDSP_PROC 0 105 #define SLAVE_CDSP_MEM_NOC 1 106 107 #define MASTER_PCIE_ANOC_CFG 0 108 #define MASTER_PCIE_0 1 109 #define MASTER_PCIE_1 2 110 #define SLAVE_ANOC_PCIE_GEM_NOC 3 111 #define SLAVE_SERVICE_PCIE_ANOC 4 112 113 #define MASTER_CFG_CENTER 0 114 #define MASTER_CFG_EAST 1 115 #define MASTER_CFG_MM 2 116 #define MASTER_CFG_NORTH 3 117 #define MASTER_CFG_SOUTH 4 118 #define MASTER_CFG_SOUTHWEST 5 119 #define SLAVE_AHB2PHY_SOUTH 6 120 #define SLAVE_BOOT_ROM 7 121 #define SLAVE_CAMERA_CFG 8 122 #define SLAVE_CLK_CTL 9 123 #define SLAVE_CRYPTO_CFG 10 124 #define SLAVE_DISPLAY_CFG 11 125 #define SLAVE_EVA_CFG 12 126 #define SLAVE_GFX3D_CFG 13 127 #define SLAVE_I2C 14 128 #define SLAVE_IMEM_CFG 15 129 #define SLAVE_IPC_ROUTER_CFG 16 130 #define SLAVE_IRIS_CFG 17 131 #define SLAVE_CNOC_MSS 18 132 #define SLAVE_PCIE_0_CFG 19 133 #define SLAVE_PCIE_1_CFG 20 134 #define SLAVE_PRNG 21 135 #define SLAVE_QSPI_0 22 136 #define SLAVE_QUP_1 23 137 #define SLAVE_QUP_2 24 138 #define SLAVE_QUP_3 25 139 #define SLAVE_QUP_4 26 140 #define SLAVE_SDCC_2 27 141 #define SLAVE_SDCC_4 28 142 #define SLAVE_TLMM 29 143 #define SLAVE_UFS_MEM_CFG 30 144 #define SLAVE_USB3 31 145 #define SLAVE_VSENSE_CTRL_CFG 32 146 #define SLAVE_PCIE_ANOC_CFG 33 147 #define SLAVE_QDSS_CFG 34 148 #define SLAVE_QDSS_STM 35 149 #define SLAVE_TCSR 36 150 #define SLAVE_TCU 37 151 152 #define MASTER_CNOC_STARDUST 0 153 #define SLAVE_STARDUST_CENTER_CFG 1 154 #define SLAVE_STARDUST_EAST_CFG 2 155 #define SLAVE_STARDUST_MM_CFG 3 156 #define SLAVE_STARDUST_NORTH_CFG 4 157 #define SLAVE_STARDUST_SOUTH_CFG 5 158 #define SLAVE_STARDUST_SOUTHWEST_CFG 6 159 160 #define MASTER_A1NOC_SNOC 0 161 #define MASTER_APSS_NOC 1 162 #define MASTER_CNOC_SNOC 2 163 #define SLAVE_SNOC_GEM_NOC_SF 3 164 165 #endif 166