1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (C) Stefan Dösinger. 4 */ 5 6 #ifndef __DT_BINDINGS_CLOCK_ZX297520V3_H 7 #define __DT_BINDINGS_CLOCK_ZX297520V3_H 8 9 #define ZX297520V3_M0_WCLK 0 10 #define ZX297520V3_SRAM1_PCLK 1 11 #define ZX297520V3_SRAM2_PCLK 2 12 #define ZX297520V3_UART0_WCLK 3 13 #define ZX297520V3_UART0_PCLK 4 14 #define ZX297520V3_I2C0_WCLK 5 15 #define ZX297520V3_I2C0_PCLK 6 16 #define ZX297520V3_RTC_WCLK 7 17 #define ZX297520V3_RTC_PCLK 8 18 #define ZX297520V3_LPM_GSM_WCLK 9 19 #define ZX297520V3_LPM_GSM_PCLK 10 20 #define ZX297520V3_LPM_LTE_WCLK 11 21 #define ZX297520V3_LPM_LTE_PCLK 12 22 #define ZX297520V3_LPM_TD_WCLK 13 23 #define ZX297520V3_LPM_TD_PCLK 14 24 #define ZX297520V3_LPM_W_WCLK 15 25 #define ZX297520V3_LPM_W_PCLK 16 26 #define ZX297520V3_TIMER_T08_WCLK 17 27 #define ZX297520V3_TIMER_T08_PCLK 18 28 #define ZX297520V3_TIMER_T09_WCLK 19 29 #define ZX297520V3_TIMER_T09_PCLK 20 30 #define ZX297520V3_MPLL 21 31 #define ZX297520V3_MPLL_D5 22 32 #define ZX297520V3_DPLL 23 33 #define ZX297520V3_GPLL 24 34 #define ZX297520V3_GPLL_D2 25 35 #define ZX297520V3_GATED_OSC26M 26 36 #define ZX297520V3_PMM_WCLK 27 37 #define ZX297520V3_PMM_PCLK 28 38 #define ZX297520V3_OUT0_WCLK 29 39 #define ZX297520V3_OUT1_WCLK 30 40 #define ZX297520V3_OUT2_WCLK 31 41 #define ZX297520V3_OUT32K_WCLK 32 42 #define ZX297520V3_RMIIPHY_WCLK 33 43 #define ZX297520V3_TIMER_T12_WCLK 34 44 #define ZX297520V3_TIMER_T12_PCLK 35 45 #define ZX297520V3_TIMER_T13_WCLK 36 46 #define ZX297520V3_TIMER_T13_PCLK 37 47 #define ZX297520V3_TIMER_T14_WCLK 38 48 #define ZX297520V3_TIMER_T14_PCLK 39 49 #define ZX297520V3_TIMER_T15_WCLK 40 50 #define ZX297520V3_TIMER_T15_PCLK 41 51 #define ZX297520V3_TIMER_T16_WCLK 42 52 #define ZX297520V3_TIMER_T16_PCLK 43 53 #define ZX297520V3_TIMER_T17_WCLK 44 54 #define ZX297520V3_TIMER_T17_PCLK 45 55 #define ZX297520V3_WDT_T18_WCLK 46 56 #define ZX297520V3_WDT_T18_PCLK 47 57 #define ZX297520V3_USIM1_WCLK 48 58 #define ZX297520V3_USIM1_PCLK 49 59 #define ZX297520V3_AHB_WCLK 50 60 #define ZX297520V3_AHB_PCLK 51 61 #define ZX297520V3_USB_WCLK 52 62 #define ZX297520V3_USB_PCLK 53 63 #define ZX297520V3_HSIC_WCLK 54 64 #define ZX297520V3_HSIC_PCLK 55 65 #define ZX297520V3_GSM_32K 56 66 #define ZX297520V3_GSM_26M 57 67 #define ZX297520V3_GSM_48M 58 68 #define ZX297520V3_GSM_104M 59 69 #define ZX297520V3_GSM_156M 60 70 #define ZX297520V3_ABB_WCLK 61 71 72 #define ZX297520V3_SYS_TIMER_WCLK 0 73 #define ZX297520V3_CPU_WCLK 1 74 #define ZX297520V3_CPU_PCLK 2 75 #define ZX297520V3_ZSP_WCLK 3 76 #define ZX297520V3_ZSP_PCLK 4 77 #define ZX297520V3_DDR_CTRL_PCLK 5 78 #define ZX297520V3_DDR_CTRL_WCLK 6 79 #define ZX297520V3_EDCP_WCLK 7 80 #define ZX297520V3_EDCP_PCLK 8 81 #define ZX297520V3_SD0_WCLK 9 82 #define ZX297520V3_SD0_PCLK 10 83 #define ZX297520V3_SD0_CDET 11 84 #define ZX297520V3_SD1_WCLK 12 85 #define ZX297520V3_SD1_PCLK 13 86 #define ZX297520V3_SD1_CDET 14 87 #define ZX297520V3_NAND_WCLK 15 88 #define ZX297520V3_NAND_PCLK 16 89 #define ZX297520V3_DMA_PCLK 17 90 #define ZX297520V3_MBOX_PCLK 18 91 #define ZX297520V3_PDCFG_WCLK 19 92 #define ZX297520V3_PDCFG_PCLK 20 93 #define ZX297520V3_RFFE_WCLK 21 94 #define ZX297520V3_SSC_WCLK 22 95 #define ZX297520V3_SSC_PCLK 23 96 #define ZX297520V3_AXI_WCLK 24 97 #define ZX297520V3_GMAC_WCLK 25 98 #define ZX297520V3_GMAC_PCLK 26 99 #define ZX297520V3_GMAC_AHB 27 100 #define ZX297520V3_VOU_WCLK 28 101 #define ZX297520V3_VOU_PCLK 29 102 #define ZX297520V3_LSP_MPLL_D5_WCLK 30 103 #define ZX297520V3_LSP_MPLL_D4_WCLK 31 104 #define ZX297520V3_LSP_MPLL_D6_WCLK 32 105 #define ZX297520V3_LSP_MPLL_D8_WCLK 33 106 #define ZX297520V3_LSP_MPLL_D12_WCLK 34 107 #define ZX297520V3_LSP_OSC26M_WCLK 35 108 #define ZX297520V3_LSP_OSC32K_WCLK 36 109 #define ZX297520V3_LSP_PCLK 37 110 #define ZX297520V3_LSP_TDM_WCLK 38 111 #define ZX297520V3_LSP_DPLL_D4_WCLK 39 112 #define ZX297520V3_SRAM0_PCLK 40 113 #define ZX297520V3_GSM_CFG_PCLK 41 114 #define ZX297520V3_LTE_MODEM_WCLK 42 115 #define ZX297520V3_LTE_MODEM_PCLK 43 116 117 #define ZX297520V3_TIMER_L1_WCLK 0 118 #define ZX297520V3_TIMER_L1_PCLK 1 119 #define ZX297520V3_WDT_L2_WCLK 2 120 #define ZX297520V3_WDT_L2_PCLK 3 121 #define ZX297520V3_WDT_L3_WCLK 4 122 #define ZX297520V3_WDT_L3_PCLK 5 123 #define ZX297520V3_PWM_WCLK 6 124 #define ZX297520V3_PWM_PCLK 7 125 #define ZX297520V3_I2S0_WCLK 8 126 #define ZX297520V3_I2S0_PCLK 9 127 #define ZX297520V3_I2S1_WCLK 10 128 #define ZX297520V3_I2S1_PCLK 11 129 #define ZX297520V3_QSPI_WCLK 12 130 #define ZX297520V3_QSPI_PCLK 13 131 #define ZX297520V3_UART1_WCLK 14 132 #define ZX297520V3_UART1_PCLK 15 133 #define ZX297520V3_I2C1_WCLK 16 134 #define ZX297520V3_I2C1_PCLK 17 135 #define ZX297520V3_SPI0_WCLK 18 136 #define ZX297520V3_SPI0_PCLK 19 137 #define ZX297520V3_TIMER_LB_WCLK 20 138 #define ZX297520V3_TIMER_LB_PCLK 21 139 #define ZX297520V3_TIMER_LC_WCLK 22 140 #define ZX297520V3_TIMER_LC_PCLK 23 141 #define ZX297520V3_UART2_WCLK 24 142 #define ZX297520V3_UART2_PCLK 25 143 #define ZX297520V3_WDT_LE_WCLK 26 144 #define ZX297520V3_WDT_LE_PCLK 27 145 #define ZX297520V3_TIMER_LF_WCLK 28 146 #define ZX297520V3_TIMER_LF_PCLK 29 147 #define ZX297520V3_SPI1_WCLK 30 148 #define ZX297520V3_SPI1_PCLK 31 149 #define ZX297520V3_TIMER_L11_WCLK 32 150 #define ZX297520V3_TIMER_L11_PCLK 33 151 #define ZX297520V3_TDM_WCLK 34 152 #define ZX297520V3_TDM_PCLK 35 153 154 #endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */ 155