1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Tenstorrent Atlantis PRCM Clock and Reset Indices 4 * 5 * Copyright (c) 2026 Tenstorrent 6 */ 7 8 #ifndef _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H 9 #define _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H 10 11 /* 12 * RCPU Domain Clock IDs 13 */ 14 #define CLK_RCPU_PLL 0 15 #define CLK_RCPU_ROOT 1 16 #define CLK_RCPU_DIV2 2 17 #define CLK_RCPU_DIV4 3 18 #define CLK_RCPU_RTC 4 19 #define CLK_SMNDMA0_ACLK 5 20 #define CLK_SMNDMA1_ACLK 6 21 #define CLK_WDT0_PCLK 7 22 #define CLK_WDT1_PCLK 8 23 #define CLK_TIMER_PCLK 9 24 #define CLK_PVTC_PCLK 10 25 #define CLK_PMU_PCLK 11 26 #define CLK_MAILBOX_HCLK 12 27 #define CLK_SEC_SPACC_HCLK 13 28 #define CLK_SEC_OTP_HCLK 14 29 #define CLK_TRNG_PCLK 15 30 #define CLK_SEC_CRC_HCLK 16 31 #define CLK_SMN_HCLK 17 32 #define CLK_AHB0_HCLK 18 33 #define CLK_SMN_PCLK 19 34 #define CLK_SMN_CLK 20 35 #define CLK_SCRATCHPAD_CLK 21 36 #define CLK_RCPU_CORE_CLK 22 37 #define CLK_RCPU_ROM_CLK 23 38 #define CLK_OTP_LOAD_CLK 24 39 #define CLK_NOC_PLL 25 40 #define CLK_NOCC_CLK 26 41 #define CLK_NOCC_DIV2 27 42 #define CLK_NOCC_DIV4 28 43 #define CLK_NOCC_RTC 29 44 #define CLK_NOCC_CAN 30 45 #define CLK_QSPI_SCLK 31 46 #define CLK_QSPI_HCLK 32 47 #define CLK_I2C0_PCLK 33 48 #define CLK_I2C1_PCLK 34 49 #define CLK_I2C2_PCLK 35 50 #define CLK_I2C3_PCLK 36 51 #define CLK_I2C4_PCLK 37 52 #define CLK_UART0_PCLK 38 53 #define CLK_UART1_PCLK 39 54 #define CLK_UART2_PCLK 40 55 #define CLK_UART3_PCLK 41 56 #define CLK_UART4_PCLK 42 57 #define CLK_SPI0_PCLK 43 58 #define CLK_SPI1_PCLK 44 59 #define CLK_SPI2_PCLK 45 60 #define CLK_SPI3_PCLK 46 61 #define CLK_GPIO_PCLK 47 62 #define CLK_CAN0_HCLK 48 63 #define CLK_CAN0_CLK 49 64 #define CLK_CAN1_HCLK 50 65 #define CLK_CAN1_CLK 51 66 #define CLK_CAN0_TIMER_CLK 52 67 #define CLK_CAN1_TIMER_CLK 53 68 69 /* RCPU domain reset */ 70 #define RST_SMNDMA0 0 71 #define RST_SMNDMA1 1 72 #define RST_WDT0 2 73 #define RST_WDT1 3 74 #define RST_TMR 4 75 #define RST_PVTC 5 76 #define RST_PMU 6 77 #define RST_MAILBOX 7 78 #define RST_SPACC 8 79 #define RST_OTP 9 80 #define RST_TRNG 10 81 #define RST_CRC 11 82 #define RST_QSPI 12 83 #define RST_I2C0 13 84 #define RST_I2C1 14 85 #define RST_I2C2 15 86 #define RST_I2C3 16 87 #define RST_I2C4 17 88 #define RST_UART0 18 89 #define RST_UART1 19 90 #define RST_UART2 20 91 #define RST_UART3 21 92 #define RST_UART4 22 93 #define RST_SPI0 23 94 #define RST_SPI1 24 95 #define RST_SPI2 25 96 #define RST_SPI3 26 97 #define RST_GPIO 27 98 #define RST_CAN0 28 99 #define RST_CAN1 29 100 #define RST_I2S0 30 101 #define RST_I2S1 31 102 103 #endif /* _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H */ 104