1 /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H 9 10 /* pll clocks */ 11 #define PLL_APLL 0 12 #define PLL_DPLL 1 13 #define PLL_CPLL 2 14 #define PLL_GPLL 3 15 #define ARMCLK 4 16 17 /* clk (clocks) */ 18 #define PCLK_DDRPHY 5 19 #define PCLK_DDR_ROOT 6 20 #define PCLK_DDRMON 7 21 #define CLK_TIMER_DDRMON 8 22 #define PCLK_DDRC 9 23 #define PCLK_DFICTRL 10 24 #define ACLK_DDR_ROOT 11 25 #define ACLK_SYS_SHRM 12 26 #define HCLK_NPU_ROOT 13 27 #define ACLK_NPU_ROOT 14 28 #define PCLK_NPU_ROOT 15 29 #define HCLK_RKNN 16 30 #define ACLK_RKNN 17 31 #define PCLK_ACODEC 18 32 #define MCLK_ACODEC_TX 19 33 #define CLK_CORE_CRYPTO 20 34 #define CLK_PKA_CRYPTO 21 35 #define ACLK_CRYPTO 22 36 #define HCLK_CRYPTO 23 37 #define ACLK_DECOM 24 38 #define PCLK_DECOM 25 39 #define DCLK_DECOM 26 40 #define ACLK_DMAC 27 41 #define PCLK_DSM 28 42 #define MCLK_DSM 29 43 #define CCLK_SRC_EMMC 30 44 #define HCLK_EMMC 31 45 #define PCLK_GPIO4 32 46 #define DBCLK_GPIO4 33 47 #define PCLK_I2C0 34 48 #define CLK_I2C0 35 49 #define PCLK_I2C2 36 50 #define CLK_I2C2 37 51 #define PCLK_I2C3 38 52 #define CLK_I2C3 39 53 #define PCLK_I2C4 40 54 #define CLK_I2C4 41 55 #define HCLK_I2S0 42 56 #define PCLK_DFT2APB 43 57 #define HCLK_IVE 44 58 #define ACLK_IVE 45 59 #define PCLK_PWM0_PERI 46 60 #define CLK_PWM0_PERI 47 61 #define CLK_CAPTURE_PWM0_PERI 48 62 #define PCLK_PERI_ROOT 49 63 #define ACLK_PERI_ROOT 50 64 #define HCLK_PERI_ROOT 51 65 #define CLK_TIMER_ROOT 52 66 #define ACLK_BUS_ROOT 53 67 #define HCLK_SFC 54 68 #define SCLK_SFC 55 69 #define PCLK_UART0 56 70 #define CLK_PVTM_CORE 57 71 #define PCLK_UART1 58 72 #define CLK_CORE_MCU_RTC 59 73 #define PCLK_PWM1_PERI 60 74 #define CLK_PWM1_PERI 61 75 #define CLK_CAPTURE_PWM1_PERI 62 76 #define PCLK_PWM2_PERI 63 77 #define CLK_PWM2_PERI 64 78 #define CLK_CAPTURE_PWM2_PERI 65 79 #define HCLK_BOOTROM 66 80 #define HCLK_SAI 67 81 #define MCLK_SAI 68 82 #define PCLK_SARADC 69 83 #define CLK_SARADC 70 84 #define PCLK_SPI1 71 85 #define CLK_SPI1 72 86 #define PCLK_STIMER 73 87 #define CLK_STIMER0 74 88 #define CLK_STIMER1 75 89 #define PCLK_TIMER 76 90 #define CLK_TIMER0 77 91 #define CLK_TIMER1 78 92 #define CLK_TIMER2 79 93 #define CLK_TIMER3 80 94 #define CLK_TIMER4 81 95 #define CLK_TIMER5 82 96 #define HCLK_TRNG_NS 83 97 #define HCLK_TRNG_S 84 98 #define PCLK_UART2 85 99 #define HCLK_CPU 86 100 #define PCLK_UART3 87 101 #define CLK_CORE_MCU 88 102 #define PCLK_UART4 89 103 #define PCLK_DDR_HWLP 90 104 #define PCLK_UART5 91 105 #define ACLK_USBOTG 92 106 #define CLK_REF_USBOTG 93 107 #define CLK_UTMI_USBOTG 94 108 #define PCLK_USBPHY 95 109 #define CLK_REF_USBPHY 96 110 #define PCLK_WDT_NS 97 111 #define TCLK_WDT_NS 98 112 #define PCLK_WDT_S 99 113 #define TCLK_WDT_S 100 114 #define CLK_DDR_FAIL_SAFE 101 115 #define XIN_OSC0_DIV 102 116 #define CLK_DEEPSLOW 103 117 #define PCLK_PMU_GPIO0 104 118 #define DBCLK_PMU_GPIO0 105 119 #define CLK_PMU 106 120 #define PCLK_PMU 107 121 #define PCLK_PMU_HP_TIMER 108 122 #define CLK_PMU_HP_TIMER 109 123 #define CLK_PMU_32K_HP_TIMER 110 124 #define PCLK_I2C1 111 125 #define CLK_I2C1 112 126 #define PCLK_PMU_IOC 113 127 #define PCLK_PMU_MAILBOX 114 128 #define CLK_PMU_MCU 115 129 #define CLK_PMU_MCU_RTC 116 130 #define CLK_PMU_MCU_JTAG 117 131 #define CLK_PVTM_PMU 118 132 #define PCLK_PVTM_PMU 119 133 #define CLK_REFOUT 120 134 #define CLK_100M_PMU 121 135 #define PCLK_PMU_ROOT 122 136 #define HCLK_PMU_ROOT 123 137 #define HCLK_PMU_SRAM 124 138 #define PCLK_PMU_WDT 125 139 #define TCLK_PMU_WDT 126 140 #define CLK_DFICTRL 127 141 #define CLK_DDRMON 128 142 #define CLK_DDR_PHY 129 143 #define ACLK_DDRC 130 144 #define CLK_CORE_DDRC_SRC 131 145 #define CLK_CORE_DDRC 132 146 #define CLK_50M_SRC 133 147 #define CLK_100M_SRC 134 148 #define CLK_150M_SRC 135 149 #define CLK_200M_SRC 136 150 #define CLK_250M_SRC 137 151 #define CLK_300M_SRC 138 152 #define CLK_339M_SRC 139 153 #define CLK_400M_SRC 140 154 #define CLK_450M_SRC 141 155 #define CLK_500M_SRC 142 156 #define CLK_I2S0_8CH_TX_SRC 143 157 #define CLK_I2S0_8CH_TX_FRAC 144 158 #define CLK_I2S0_8CH_TX 145 159 #define CLK_I2S0_8CH_RX_SRC 146 160 #define CLK_I2S0_8CH_RX_FRAC 147 161 #define CLK_I2S0_8CH_RX 148 162 #define I2S0_8CH_MCLKOUT 149 163 #define MCLK_I2S0_8CH_RX 150 164 #define MCLK_I2S0_8CH_TX 151 165 #define CLK_REF_MIPI0_SRC 152 166 #define CLK_REF_MIPI0_FRAC 153 167 #define CLK_REF_MIPI0_OUT 154 168 #define CLK_REF_MIPI1_SRC 155 169 #define CLK_REF_MIPI1_FRAC 156 170 #define MCLK_REF_MIPI0 157 171 #define MCLK_REF_MIPI1 158 172 #define CLK_REF_MIPI0 159 173 #define CLK_REF_MIPI1 160 174 #define CLK_UART0_SRC 161 175 #define CLK_UART0_FRAC 162 176 #define CLK_UART0 163 177 #define SCLK_UART0 164 178 #define CLK_UART1_SRC 165 179 #define CLK_UART1_FRAC 166 180 #define CLK_UART1 167 181 #define SCLK_UART1 168 182 #define CLK_UART2_SRC 169 183 #define CLK_UART2_FRAC 170 184 #define CLK_UART2 171 185 #define SCLK_UART2 172 186 #define CLK_UART3_SRC 173 187 #define CLK_UART3_FRAC 174 188 #define CLK_UART3 175 189 #define SCLK_UART3 176 190 #define CLK_UART4_SRC 177 191 #define CLK_UART4_FRAC 178 192 #define CLK_UART4 179 193 #define SCLK_UART4 180 194 #define CLK_UART5_SRC 181 195 #define CLK_UART5_FRAC 182 196 #define CLK_UART5 183 197 #define SCLK_UART5 184 198 #define CLK_VICAP_M0_SRC 185 199 #define CLK_VICAP_M0_FRAC 186 200 #define CLK_VICAP_M0 187 201 #define SCLK_VICAP_M0 188 202 #define CLK_VICAP_M1_SRC 189 203 #define CLK_VICAP_M1_FRAC 190 204 #define CLK_VICAP_M1 191 205 #define SCLK_VICAP_M1 192 206 #define DCLK_VOP_SRC 193 207 #define PCLK_CRU 194 208 #define PCLK_TOP_ROOT 195 209 #define PCLK_SPI0 196 210 #define CLK_SPI0 197 211 #define SCLK_IN_SPI0 198 212 #define CLK_UART_DETN_FLT 199 213 #define HCLK_VEPU 200 214 #define ACLK_VEPU 201 215 #define CLK_CORE_VEPU 202 216 #define CLK_CORE_VEPU_DVBM 203 217 #define PCLK_GPIO1 204 218 #define DBCLK_GPIO1 205 219 #define HCLK_VEPU_PP 206 220 #define ACLK_VEPU_PP 207 221 #define HCLK_VEPU_ROOT 208 222 #define ACLK_VEPU_COM_ROOT 209 223 #define ACLK_VEPU_ROOT 210 224 #define PCLK_VEPU_ROOT 211 225 #define PCLK_VICAP_VEPU 212 226 #define PCLK_CSIHOST0 213 227 #define CLK_RXBYTECLKHS_0 214 228 #define PCLK_CSIHOST1 215 229 #define CLK_RXBYTECLKHS_1 216 230 #define PCLK_GPIO3 217 231 #define DBCLK_GPIO3 218 232 #define HCLK_ISP3P2 219 233 #define ACLK_ISP3P2 220 234 #define CLK_CORE_ISP3P2 221 235 #define PCLK_MIPICSIPHY 222 236 #define CCLK_SRC_SDMMC 223 237 #define HCLK_SDMMC 224 238 #define CLK_SDMMC_DETN_FLT 225 239 #define HCLK_VI_ROOT 226 240 #define ACLK_VI_ROOT 227 241 #define PCLK_VI_ROOT 228 242 #define PCLK_VI_RTC_ROOT 229 243 #define PCLK_VI_RTC_TEST 230 244 #define PCLK_VI_RTC_PHY 231 245 #define DCLK_VICAP 232 246 #define PCLK_VICAP 233 247 #define ACLK_VICAP 234 248 #define HCLK_VICAP 235 249 #define I0CLK_VICAP 236 250 #define I1CLK_VICAP 237 251 #define RX0PCLK_VICAP 238 252 #define RX1PCLK_VICAP 239 253 #define ISP0CLK_VICAP 240 254 #define PCLK_GPIO2 241 255 #define DBCLK_GPIO2 242 256 #define ACLK_MAC 243 257 #define PCLK_MAC 244 258 #define CLK_GMAC0_50M_O 245 259 #define CLK_GMAC0_TX_50M_O 246 260 #define CLK_GMAC0_REF_50M 247 261 #define CLK_GMAC0_TX_50M 248 262 #define CLK_GMAC0_RX_50M 249 263 #define ACLK_MAC_ROOT 250 264 #define CLK_MACPHY 251 265 #define CLK_OTPC_ARB 252 266 #define PCLK_OTPC_NS 253 267 #define CLK_SBPI_OTPC_NS 254 268 #define CLK_USER_OTPC_NS 255 269 #define PCLK_OTPC_S 256 270 #define CLK_SBPI_OTPC_S 257 271 #define CLK_USER_OTPC_S 258 272 #define PCLK_OTP_MASK 259 273 #define CLK_PMC_OTP 260 274 #define HCLK_RGA2E 261 275 #define ACLK_RGA2E 262 276 #define CLK_CORE_RGA2E 263 277 #define CCLK_SRC_SDIO 264 278 #define HCLK_SDIO 265 279 #define PCLK_TSADC 266 280 #define CLK_TSADC 267 281 #define CLK_TSADC_TSEN 268 282 #define ACLK_VO_ROOT 269 283 #define HCLK_VO_ROOT 270 284 #define PCLK_VO_ROOT 271 285 #define ACLK_VOP_ROOT 272 286 #define HCLK_VOP 273 287 #define DCLK_VOP 274 288 #define ACLK_VOP 275 289 #define CLK_RTC_32K 276 290 #define PCLK_MAILBOX 277 291 292 /* mmc phase clocks */ 293 #define SCLK_EMMC_DRV 278 294 #define SCLK_EMMC_SAMPLE 279 295 #define SCLK_SDMMC_DRV 280 296 #define SCLK_SDMMC_SAMPLE 281 297 #define SCLK_SDIO_DRV 282 298 #define SCLK_SDIO_SAMPLE 283 299 300 /* internal clocks */ 301 #define XIN_OSC0_HALF 284 302 #define PCLK_DBG 285 303 #define PCLK_CPU_ROOT 286 304 #define CLK_RTC32K_FRAC 287 305 306 #endif 307