1 /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> 5 * Author: Joseph Chen <chenjh@rock-chips.com> 6 */ 7 8 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H 9 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H 10 11 /* cru-clocks indices */ 12 #define PLL_APLL 0 13 #define PLL_CPLL 1 14 #define PLL_GPLL 2 15 #define PLL_PPLL 3 16 #define PLL_DPLL 4 17 #define ARMCLK 5 18 #define XIN_OSC0_HALF 6 19 #define CLK_MATRIX_50M_SRC 7 20 #define CLK_MATRIX_100M_SRC 8 21 #define CLK_MATRIX_150M_SRC 9 22 #define CLK_MATRIX_200M_SRC 10 23 #define CLK_MATRIX_250M_SRC 11 24 #define CLK_MATRIX_300M_SRC 12 25 #define CLK_MATRIX_339M_SRC 13 26 #define CLK_MATRIX_400M_SRC 14 27 #define CLK_MATRIX_500M_SRC 15 28 #define CLK_MATRIX_600M_SRC 16 29 #define CLK_UART0_SRC 17 30 #define CLK_UART0_FRAC 18 31 #define SCLK_UART0 19 32 #define CLK_UART1_SRC 20 33 #define CLK_UART1_FRAC 21 34 #define SCLK_UART1 22 35 #define CLK_UART2_SRC 23 36 #define CLK_UART2_FRAC 24 37 #define SCLK_UART2 25 38 #define CLK_UART3_SRC 26 39 #define CLK_UART3_FRAC 27 40 #define SCLK_UART3 28 41 #define CLK_UART4_SRC 29 42 #define CLK_UART4_FRAC 30 43 #define SCLK_UART4 31 44 #define CLK_UART5_SRC 32 45 #define CLK_UART5_FRAC 33 46 #define SCLK_UART5 34 47 #define CLK_UART6_SRC 35 48 #define CLK_UART6_FRAC 36 49 #define SCLK_UART6 37 50 #define CLK_UART7_SRC 38 51 #define CLK_UART7_FRAC 39 52 #define SCLK_UART7 40 53 #define CLK_I2S0_2CH_SRC 41 54 #define CLK_I2S0_2CH_FRAC 42 55 #define MCLK_I2S0_2CH_SAI_SRC 43 56 #define CLK_I2S3_8CH_SRC 44 57 #define CLK_I2S3_8CH_FRAC 45 58 #define MCLK_I2S3_8CH_SAI_SRC 46 59 #define CLK_I2S1_8CH_SRC 47 60 #define CLK_I2S1_8CH_FRAC 48 61 #define MCLK_I2S1_8CH_SAI_SRC 49 62 #define CLK_I2S2_2CH_SRC 50 63 #define CLK_I2S2_2CH_FRAC 51 64 #define MCLK_I2S2_2CH_SAI_SRC 52 65 #define CLK_SPDIF_SRC 53 66 #define CLK_SPDIF_FRAC 54 67 #define MCLK_SPDIF_SRC 55 68 #define DCLK_VOP_SRC0 56 69 #define DCLK_VOP_SRC1 57 70 #define CLK_HSM 58 71 #define CLK_CORE_SRC_ACS 59 72 #define CLK_CORE_SRC_PVTMUX 60 73 #define CLK_CORE_SRC 61 74 #define CLK_CORE 62 75 #define ACLK_M_CORE_BIU 63 76 #define CLK_CORE_PVTPLL_SRC 64 77 #define PCLK_DBG 65 78 #define SWCLKTCK 66 79 #define CLK_SCANHS_CORE 67 80 #define CLK_SCANHS_ACLKM_CORE 68 81 #define CLK_SCANHS_PCLK_DBG 69 82 #define CLK_SCANHS_PCLK_CPU_BIU 70 83 #define PCLK_CPU_ROOT 71 84 #define PCLK_CORE_GRF 72 85 #define PCLK_DAPLITE_BIU 73 86 #define PCLK_CPU_BIU 74 87 #define CLK_REF_PVTPLL_CORE 75 88 #define ACLK_BUS_VOPGL_ROOT 76 89 #define ACLK_BUS_VOPGL_BIU 77 90 #define ACLK_BUS_H_ROOT 78 91 #define ACLK_BUS_H_BIU 79 92 #define ACLK_BUS_ROOT 80 93 #define HCLK_BUS_ROOT 81 94 #define PCLK_BUS_ROOT 82 95 #define ACLK_BUS_M_ROOT 83 96 #define ACLK_SYSMEM_BIU 84 97 #define CLK_TIMER_ROOT 85 98 #define ACLK_BUS_BIU 86 99 #define HCLK_BUS_BIU 87 100 #define PCLK_BUS_BIU 88 101 #define PCLK_DFT2APB 89 102 #define PCLK_BUS_GRF 90 103 #define ACLK_BUS_M_BIU 91 104 #define ACLK_GIC 92 105 #define ACLK_SPINLOCK 93 106 #define ACLK_DMAC 94 107 #define PCLK_TIMER 95 108 #define CLK_TIMER0 96 109 #define CLK_TIMER1 97 110 #define CLK_TIMER2 98 111 #define CLK_TIMER3 99 112 #define CLK_TIMER4 100 113 #define CLK_TIMER5 101 114 #define PCLK_JDBCK_DAP 102 115 #define CLK_JDBCK_DAP 103 116 #define PCLK_WDT_NS 104 117 #define TCLK_WDT_NS 105 118 #define HCLK_TRNG_NS 106 119 #define PCLK_UART0 107 120 #define PCLK_DMA2DDR 108 121 #define ACLK_DMA2DDR 109 122 #define PCLK_PWM0 110 123 #define CLK_PWM0 111 124 #define CLK_CAPTURE_PWM0 112 125 #define PCLK_PWM1 113 126 #define CLK_PWM1 114 127 #define CLK_CAPTURE_PWM1 115 128 #define PCLK_SCR 116 129 #define ACLK_DCF 117 130 #define PCLK_INTMUX 118 131 #define CLK_PPLL_I 119 132 #define CLK_PPLL_MUX 120 133 #define CLK_PPLL_100M_MATRIX 121 134 #define CLK_PPLL_50M_MATRIX 122 135 #define CLK_REF_PCIE_INNER_PHY 123 136 #define CLK_REF_PCIE_100M_PHY 124 137 #define ACLK_VPU_L_ROOT 125 138 #define CLK_GMAC1_VPU_25M 126 139 #define CLK_PPLL_125M_MATRIX 127 140 #define ACLK_VPU_ROOT 128 141 #define HCLK_VPU_ROOT 129 142 #define PCLK_VPU_ROOT 130 143 #define ACLK_VPU_BIU 131 144 #define HCLK_VPU_BIU 132 145 #define PCLK_VPU_BIU 133 146 #define ACLK_VPU 134 147 #define HCLK_VPU 135 148 #define PCLK_CRU_PCIE 136 149 #define PCLK_VPU_GRF 137 150 #define HCLK_SFC 138 151 #define SCLK_SFC 139 152 #define CCLK_SRC_EMMC 140 153 #define HCLK_EMMC 141 154 #define ACLK_EMMC 142 155 #define BCLK_EMMC 143 156 #define TCLK_EMMC 144 157 #define PCLK_GPIO1 145 158 #define DBCLK_GPIO1 146 159 #define ACLK_VPU_L_BIU 147 160 #define PCLK_VPU_IOC 148 161 #define HCLK_SAI_I2S0 149 162 #define MCLK_SAI_I2S0 150 163 #define HCLK_SAI_I2S2 151 164 #define MCLK_SAI_I2S2 152 165 #define PCLK_ACODEC 153 166 #define MCLK_ACODEC_TX 154 167 #define PCLK_GPIO3 155 168 #define DBCLK_GPIO3 156 169 #define PCLK_SPI1 157 170 #define CLK_SPI1 158 171 #define SCLK_IN_SPI1 159 172 #define PCLK_UART2 160 173 #define PCLK_UART5 161 174 #define PCLK_UART6 162 175 #define PCLK_UART7 163 176 #define PCLK_I2C3 164 177 #define CLK_I2C3 165 178 #define PCLK_I2C5 166 179 #define CLK_I2C5 167 180 #define PCLK_I2C6 168 181 #define CLK_I2C6 169 182 #define ACLK_MAC_VPU 170 183 #define PCLK_MAC_VPU 171 184 #define CLK_GMAC1_RMII_VPU 172 185 #define CLK_GMAC1_SRC_VPU 173 186 #define PCLK_PCIE 174 187 #define CLK_PCIE_AUX 175 188 #define ACLK_PCIE 176 189 #define HCLK_PCIE_SLV 177 190 #define HCLK_PCIE_DBI 178 191 #define PCLK_PCIE_PHY 179 192 #define PCLK_PIPE_GRF 180 193 #define CLK_PIPE_USB3OTG_COMBO 181 194 #define CLK_UTMI_USB3OTG 182 195 #define CLK_PCIE_PIPE_PHY 183 196 #define CCLK_SRC_SDIO0 184 197 #define HCLK_SDIO0 185 198 #define CCLK_SRC_SDIO1 186 199 #define HCLK_SDIO1 187 200 #define CLK_TS_0 188 201 #define CLK_TS_1 189 202 #define PCLK_CAN2 190 203 #define CLK_CAN2 191 204 #define PCLK_CAN3 192 205 #define CLK_CAN3 193 206 #define PCLK_SARADC 194 207 #define CLK_SARADC 195 208 #define PCLK_TSADC 196 209 #define CLK_TSADC 197 210 #define CLK_TSADC_TSEN 198 211 #define ACLK_USB3OTG 199 212 #define CLK_REF_USB3OTG 200 213 #define CLK_SUSPEND_USB3OTG 201 214 #define ACLK_GPU_ROOT 202 215 #define PCLK_GPU_ROOT 203 216 #define ACLK_GPU_BIU 204 217 #define PCLK_GPU_BIU 205 218 #define ACLK_GPU 206 219 #define CLK_GPU_PVTPLL_SRC 207 220 #define ACLK_GPU_MALI 208 221 #define HCLK_RKVENC_ROOT 209 222 #define ACLK_RKVENC_ROOT 210 223 #define PCLK_RKVENC_ROOT 211 224 #define HCLK_RKVENC_BIU 212 225 #define ACLK_RKVENC_BIU 213 226 #define PCLK_RKVENC_BIU 214 227 #define HCLK_RKVENC 215 228 #define ACLK_RKVENC 216 229 #define CLK_CORE_RKVENC 217 230 #define HCLK_SAI_I2S1 218 231 #define MCLK_SAI_I2S1 219 232 #define PCLK_I2C1 220 233 #define CLK_I2C1 221 234 #define PCLK_I2C0 222 235 #define CLK_I2C0 223 236 #define CLK_UART_JTAG 224 237 #define PCLK_SPI0 225 238 #define CLK_SPI0 226 239 #define SCLK_IN_SPI0 227 240 #define PCLK_GPIO4 228 241 #define DBCLK_GPIO4 229 242 #define PCLK_RKVENC_IOC 230 243 #define HCLK_SPDIF 231 244 #define MCLK_SPDIF 232 245 #define HCLK_PDM 233 246 #define MCLK_PDM 234 247 #define PCLK_UART1 235 248 #define PCLK_UART3 236 249 #define PCLK_RKVENC_GRF 237 250 #define PCLK_CAN0 238 251 #define CLK_CAN0 239 252 #define PCLK_CAN1 240 253 #define CLK_CAN1 241 254 #define ACLK_VO_ROOT 242 255 #define HCLK_VO_ROOT 243 256 #define PCLK_VO_ROOT 244 257 #define ACLK_VO_BIU 245 258 #define HCLK_VO_BIU 246 259 #define PCLK_VO_BIU 247 260 #define HCLK_RGA2E 248 261 #define ACLK_RGA2E 249 262 #define CLK_CORE_RGA2E 250 263 #define HCLK_VDPP 251 264 #define ACLK_VDPP 252 265 #define CLK_CORE_VDPP 253 266 #define PCLK_VO_GRF 254 267 #define PCLK_CRU 255 268 #define ACLK_VOP_ROOT 256 269 #define ACLK_VOP_BIU 257 270 #define HCLK_VOP 258 271 #define DCLK_VOP0 259 272 #define DCLK_VOP1 260 273 #define ACLK_VOP 261 274 #define PCLK_HDMI 262 275 #define CLK_SFR_HDMI 263 276 #define CLK_CEC_HDMI 264 277 #define CLK_SPDIF_HDMI 265 278 #define CLK_HDMIPHY_TMDSSRC 266 279 #define CLK_HDMIPHY_PREP 267 280 #define PCLK_HDMIPHY 268 281 #define HCLK_HDCP_KEY 269 282 #define ACLK_HDCP 270 283 #define HCLK_HDCP 271 284 #define PCLK_HDCP 272 285 #define HCLK_CVBS 273 286 #define DCLK_CVBS 274 287 #define DCLK_4X_CVBS 275 288 #define ACLK_JPEG_DECODER 276 289 #define HCLK_JPEG_DECODER 277 290 #define ACLK_VO_L_ROOT 278 291 #define ACLK_VO_L_BIU 279 292 #define ACLK_MAC_VO 280 293 #define PCLK_MAC_VO 281 294 #define CLK_GMAC0_SRC 282 295 #define CLK_GMAC0_RMII_50M 283 296 #define CLK_GMAC0_TX 284 297 #define CLK_GMAC0_RX 285 298 #define ACLK_JPEG_ROOT 286 299 #define ACLK_JPEG_BIU 287 300 #define HCLK_SAI_I2S3 288 301 #define MCLK_SAI_I2S3 289 302 #define CLK_MACPHY 290 303 #define PCLK_VCDCPHY 291 304 #define PCLK_GPIO2 292 305 #define DBCLK_GPIO2 293 306 #define PCLK_VO_IOC 294 307 #define CCLK_SRC_SDMMC0 295 308 #define HCLK_SDMMC0 296 309 #define PCLK_OTPC_NS 297 310 #define CLK_SBPI_OTPC_NS 298 311 #define CLK_USER_OTPC_NS 299 312 #define CLK_HDMIHDP0 300 313 #define HCLK_USBHOST 301 314 #define HCLK_USBHOST_ARB 302 315 #define CLK_USBHOST_OHCI 303 316 #define CLK_USBHOST_UTMI 304 317 #define PCLK_UART4 305 318 #define PCLK_I2C4 306 319 #define CLK_I2C4 307 320 #define PCLK_I2C7 308 321 #define CLK_I2C7 309 322 #define PCLK_USBPHY 310 323 #define CLK_REF_USBPHY 311 324 #define HCLK_RKVDEC_ROOT 312 325 #define ACLK_RKVDEC_ROOT_NDFT 313 326 #define PCLK_DDRPHY_CRU 314 327 #define HCLK_RKVDEC_BIU 315 328 #define ACLK_RKVDEC_BIU 316 329 #define ACLK_RKVDEC 317 330 #define HCLK_RKVDEC 318 331 #define CLK_HEVC_CA_RKVDEC 319 332 #define ACLK_RKVDEC_PVTMUX_ROOT 320 333 #define CLK_RKVDEC_PVTPLL_SRC 321 334 #define PCLK_DDR_ROOT 322 335 #define PCLK_DDR_BIU 323 336 #define PCLK_DDRC 324 337 #define PCLK_DDRMON 325 338 #define CLK_TIMER_DDRMON 326 339 #define PCLK_MSCH_BIU 327 340 #define PCLK_DDR_GRF 328 341 #define PCLK_DDR_HWLP 329 342 #define PCLK_DDRPHY 330 343 #define CLK_MSCH_BIU 331 344 #define ACLK_DDR_UPCTL 332 345 #define CLK_DDR_UPCTL 333 346 #define CLK_DDRMON 334 347 #define ACLK_DDR_SCRAMBLE 335 348 #define ACLK_SPLIT 336 349 #define CLK_DDRC_SRC 337 350 #define CLK_DDR_PHY 338 351 #define PCLK_OTPC_S 339 352 #define CLK_SBPI_OTPC_S 340 353 #define CLK_USER_OTPC_S 341 354 #define PCLK_KEYREADER 342 355 #define PCLK_BUS_SGRF 343 356 #define PCLK_STIMER 344 357 #define CLK_STIMER0 345 358 #define CLK_STIMER1 346 359 #define PCLK_WDT_S 347 360 #define TCLK_WDT_S 348 361 #define HCLK_TRNG_S 349 362 #define HCLK_BOOTROM 350 363 #define PCLK_DCF 351 364 #define ACLK_SYSMEM 352 365 #define HCLK_TSP 353 366 #define ACLK_TSP 354 367 #define CLK_CORE_TSP 355 368 #define CLK_OTPC_ARB 356 369 #define PCLK_OTP_MASK 357 370 #define CLK_PMC_OTP 358 371 #define PCLK_PMU_ROOT 359 372 #define HCLK_PMU_ROOT 360 373 #define PCLK_I2C2 361 374 #define CLK_I2C2 362 375 #define HCLK_PMU_BIU 363 376 #define PCLK_PMU_BIU 364 377 #define FCLK_MCU 365 378 #define RTC_CLK_MCU 366 379 #define PCLK_OSCCHK 367 380 #define CLK_PMU_MCU_JTAG 368 381 #define PCLK_PMU 369 382 #define PCLK_GPIO0 370 383 #define DBCLK_GPIO0 371 384 #define XIN_OSC0_DIV 372 385 #define CLK_DEEPSLOW 373 386 #define CLK_DDR_FAIL_SAFE 374 387 #define PCLK_PMU_HP_TIMER 375 388 #define CLK_PMU_HP_TIMER 376 389 #define CLK_PMU_32K_HP_TIMER 377 390 #define PCLK_PMU_IOC 378 391 #define PCLK_PMU_CRU 379 392 #define PCLK_PMU_GRF 380 393 #define PCLK_PMU_WDT 381 394 #define TCLK_PMU_WDT 382 395 #define PCLK_PMU_MAILBOX 383 396 #define PCLK_SCRKEYGEN 384 397 #define CLK_SCRKEYGEN 385 398 #define CLK_PVTM_OSCCHK 386 399 #define CLK_REFOUT 387 400 #define CLK_PVTM_PMU 388 401 #define PCLK_PVTM_PMU 389 402 #define PCLK_PMU_SGRF 390 403 #define HCLK_PMU_SRAM 391 404 #define CLK_UART0 392 405 #define CLK_UART1 393 406 #define CLK_UART2 394 407 #define CLK_UART3 395 408 #define CLK_UART4 396 409 #define CLK_UART5 397 410 #define CLK_UART6 398 411 #define CLK_UART7 399 412 #define MCLK_I2S0_2CH_SAI_SRC_PRE 400 413 #define MCLK_I2S1_8CH_SAI_SRC_PRE 401 414 #define MCLK_I2S2_2CH_SAI_SRC_PRE 402 415 #define MCLK_I2S3_8CH_SAI_SRC_PRE 403 416 #define MCLK_SDPDIF_SRC_PRE 404 417 #define SCLK_SDMMC_DRV 405 418 #define SCLK_SDMMC_SAMPLE 406 419 #define SCLK_SDIO0_DRV 407 420 #define SCLK_SDIO0_SAMPLE 408 421 #define SCLK_SDIO1_DRV 409 422 #define SCLK_SDIO1_SAMPLE 410 423 424 /* scmi-clocks indices */ 425 #define SCMI_PCLK_KEYREADER 0 426 #define SCMI_HCLK_KLAD 1 427 #define SCMI_PCLK_KLAD 2 428 #define SCMI_HCLK_TRNG_S 3 429 #define SCMI_HCLK_CRYPTO_S 4 430 #define SCMI_PCLK_WDT_S 5 431 #define SCMI_TCLK_WDT_S 6 432 #define SCMI_PCLK_STIMER 7 433 #define SCMI_CLK_STIMER0 8 434 #define SCMI_CLK_STIMER1 9 435 #define SCMI_PCLK_OTP_MASK 10 436 #define SCMI_PCLK_OTPC_S 11 437 #define SCMI_CLK_SBPI_OTPC_S 12 438 #define SCMI_CLK_USER_OTPC_S 13 439 #define SCMI_CLK_PMC_OTP 14 440 #define SCMI_CLK_OTPC_ARB 15 441 #define SCMI_CLK_CORE_TSP 16 442 #define SCMI_ACLK_TSP 17 443 #define SCMI_HCLK_TSP 18 444 #define SCMI_PCLK_DCF 19 445 #define SCMI_CLK_DDR 20 446 #define SCMI_CLK_CPU 21 447 #define SCMI_CLK_GPU 22 448 #define SCMI_CORE_CRYPTO 23 449 #define SCMI_ACLK_CRYPTO 24 450 #define SCMI_PKA_CRYPTO 25 451 #define SCMI_HCLK_CRYPTO 26 452 #define SCMI_CORE_CRYPTO_S 27 453 #define SCMI_ACLK_CRYPTO_S 28 454 #define SCMI_PKA_CRYPTO_S 29 455 #define SCMI_CORE_KLAD 30 456 #define SCMI_ACLK_KLAD 31 457 #define SCMI_HCLK_TRNG 32 458 459 #endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H 460