1*35e3509bSLuo Jie /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*35e3509bSLuo Jie /* 3*35e3509bSLuo Jie * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4*35e3509bSLuo Jie */ 5*35e3509bSLuo Jie 6*35e3509bSLuo Jie #ifndef _DT_BINDINGS_CLK_QCOM_IPQ5332_CMN_PLL_H 7*35e3509bSLuo Jie #define _DT_BINDINGS_CLK_QCOM_IPQ5332_CMN_PLL_H 8*35e3509bSLuo Jie 9*35e3509bSLuo Jie /* CMN PLL core clock. */ 10*35e3509bSLuo Jie #define IPQ5332_CMN_PLL_CLK 0 11*35e3509bSLuo Jie 12*35e3509bSLuo Jie /* The output clocks from CMN PLL of IPQ5332. */ 13*35e3509bSLuo Jie #define IPQ5332_XO_24MHZ_CLK 1 14*35e3509bSLuo Jie #define IPQ5332_SLEEP_32KHZ_CLK 2 15*35e3509bSLuo Jie #define IPQ5332_PCS_31P25MHZ_CLK 3 16*35e3509bSLuo Jie #define IPQ5332_NSS_300MHZ_CLK 4 17*35e3509bSLuo Jie #define IPQ5332_PPE_200MHZ_CLK 5 18*35e3509bSLuo Jie #define IPQ5332_ETH_50MHZ_CLK 6 19*35e3509bSLuo Jie #endif 20