1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_X1P42100_H 7 #define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_X1P42100_H 8 9 /* VIDEO_CC clocks */ 10 #define VIDEO_CC_MVS0_CLK 0 11 #define VIDEO_CC_MVS0_CLK_SRC 1 12 #define VIDEO_CC_MVS0_DIV_CLK_SRC 2 13 #define VIDEO_CC_MVS0C_CLK 3 14 #define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4 15 #define VIDEO_CC_MVS1_CLK 5 16 #define VIDEO_CC_MVS1_CLK_SRC 6 17 #define VIDEO_CC_MVS1_DIV_CLK_SRC 7 18 #define VIDEO_CC_MVS1C_CLK 8 19 #define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9 20 #define VIDEO_CC_PLL0 10 21 #define VIDEO_CC_PLL1 11 22 #define VIDEO_CC_MVS0_SHIFT_CLK 12 23 #define VIDEO_CC_MVS0C_SHIFT_CLK 13 24 #define VIDEO_CC_MVS1_SHIFT_CLK 14 25 #define VIDEO_CC_MVS1C_SHIFT_CLK 15 26 #define VIDEO_CC_XO_CLK_SRC 16 27 #define VIDEO_CC_MVS0_BSE_CLK 17 28 #define VIDEO_CC_MVS0_BSE_CLK_SRC 18 29 #define VIDEO_CC_MVS0_BSE_DIV4_DIV_CLK_SRC 19 30 31 /* VIDEO_CC power domains */ 32 #define VIDEO_CC_MVS0C_GDSC 0 33 #define VIDEO_CC_MVS0_GDSC 1 34 #define VIDEO_CC_MVS1C_GDSC 2 35 #define VIDEO_CC_MVS1_GDSC 3 36 37 /* VIDEO_CC resets */ 38 #define CVP_VIDEO_CC_INTERFACE_BCR 0 39 #define CVP_VIDEO_CC_MVS0_BCR 1 40 #define CVP_VIDEO_CC_MVS0C_BCR 2 41 #define CVP_VIDEO_CC_MVS1_BCR 3 42 #define CVP_VIDEO_CC_MVS1C_BCR 4 43 #define VIDEO_CC_MVS0C_CLK_ARES 5 44 #define VIDEO_CC_MVS1C_CLK_ARES 6 45 #define VIDEO_CC_XO_CLK_ARES 7 46 #define VIDEO_CC_MVS0_BSE_BCR 8 47 48 #endif 49