1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H 7 #define _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H 8 9 /* SE_GCC clocks */ 10 #define SE_GCC_EEE_EMAC0_CLK 0 11 #define SE_GCC_EEE_EMAC0_CLK_SRC 1 12 #define SE_GCC_EEE_EMAC1_CLK 2 13 #define SE_GCC_EEE_EMAC1_CLK_SRC 3 14 #define SE_GCC_EMAC0_AXI_CLK 4 15 #define SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK 5 16 #define SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK 6 17 #define SE_GCC_EMAC0_PHY_AUX_CLK 7 18 #define SE_GCC_EMAC0_PHY_AUX_CLK_SRC 8 19 #define SE_GCC_EMAC0_PTP_CLK 9 20 #define SE_GCC_EMAC0_PTP_CLK_SRC 10 21 #define SE_GCC_EMAC0_RGMII_CLK 11 22 #define SE_GCC_EMAC0_RGMII_CLK_SRC 12 23 #define SE_GCC_EMAC0_RPCS_RX_CLK 13 24 #define SE_GCC_EMAC0_RPCS_TX_CLK 14 25 #define SE_GCC_EMAC0_XGXS_RX_CLK 15 26 #define SE_GCC_EMAC0_XGXS_TX_CLK 16 27 #define SE_GCC_EMAC1_AXI_CLK 17 28 #define SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK 18 29 #define SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK 19 30 #define SE_GCC_EMAC1_PHY_AUX_CLK 20 31 #define SE_GCC_EMAC1_PHY_AUX_CLK_SRC 21 32 #define SE_GCC_EMAC1_PTP_CLK 22 33 #define SE_GCC_EMAC1_PTP_CLK_SRC 23 34 #define SE_GCC_EMAC1_RGMII_CLK 24 35 #define SE_GCC_EMAC1_RGMII_CLK_SRC 25 36 #define SE_GCC_EMAC1_RPCS_RX_CLK 26 37 #define SE_GCC_EMAC1_RPCS_TX_CLK 27 38 #define SE_GCC_EMAC1_XGXS_RX_CLK 28 39 #define SE_GCC_EMAC1_XGXS_TX_CLK 29 40 #define SE_GCC_FRQ_MEASURE_REF_CLK 30 41 #define SE_GCC_GP1_CLK 31 42 #define SE_GCC_GP1_CLK_SRC 32 43 #define SE_GCC_GP2_CLK 33 44 #define SE_GCC_GP2_CLK_SRC 34 45 #define SE_GCC_GPLL0 35 46 #define SE_GCC_GPLL0_OUT_EVEN 36 47 #define SE_GCC_GPLL2 37 48 #define SE_GCC_GPLL4 38 49 #define SE_GCC_GPLL5 39 50 #define SE_GCC_MMU_2_TCU_VOTE_CLK 40 51 #define SE_GCC_QUPV3_WRAP0_CORE_2X_CLK 41 52 #define SE_GCC_QUPV3_WRAP0_CORE_CLK 42 53 #define SE_GCC_QUPV3_WRAP0_M_AHB_CLK 43 54 #define SE_GCC_QUPV3_WRAP0_S0_CLK 44 55 #define SE_GCC_QUPV3_WRAP0_S0_CLK_SRC 45 56 #define SE_GCC_QUPV3_WRAP0_S1_CLK 46 57 #define SE_GCC_QUPV3_WRAP0_S1_CLK_SRC 47 58 #define SE_GCC_QUPV3_WRAP0_S2_CLK 48 59 #define SE_GCC_QUPV3_WRAP0_S2_CLK_SRC 49 60 #define SE_GCC_QUPV3_WRAP0_S3_CLK 50 61 #define SE_GCC_QUPV3_WRAP0_S3_CLK_SRC 51 62 #define SE_GCC_QUPV3_WRAP0_S4_CLK 52 63 #define SE_GCC_QUPV3_WRAP0_S4_CLK_SRC 53 64 #define SE_GCC_QUPV3_WRAP0_S5_CLK 54 65 #define SE_GCC_QUPV3_WRAP0_S5_CLK_SRC 55 66 #define SE_GCC_QUPV3_WRAP0_S6_CLK 56 67 #define SE_GCC_QUPV3_WRAP0_S6_CLK_SRC 57 68 #define SE_GCC_QUPV3_WRAP0_S_AHB_CLK 58 69 #define SE_GCC_QUPV3_WRAP1_CORE_2X_CLK 59 70 #define SE_GCC_QUPV3_WRAP1_CORE_CLK 60 71 #define SE_GCC_QUPV3_WRAP1_M_AHB_CLK 61 72 #define SE_GCC_QUPV3_WRAP1_S0_CLK 62 73 #define SE_GCC_QUPV3_WRAP1_S0_CLK_SRC 63 74 #define SE_GCC_QUPV3_WRAP1_S1_CLK 64 75 #define SE_GCC_QUPV3_WRAP1_S1_CLK_SRC 65 76 #define SE_GCC_QUPV3_WRAP1_S2_CLK 66 77 #define SE_GCC_QUPV3_WRAP1_S2_CLK_SRC 67 78 #define SE_GCC_QUPV3_WRAP1_S3_CLK 68 79 #define SE_GCC_QUPV3_WRAP1_S3_CLK_SRC 69 80 #define SE_GCC_QUPV3_WRAP1_S4_CLK 70 81 #define SE_GCC_QUPV3_WRAP1_S4_CLK_SRC 71 82 #define SE_GCC_QUPV3_WRAP1_S5_CLK 72 83 #define SE_GCC_QUPV3_WRAP1_S5_CLK_SRC 73 84 #define SE_GCC_QUPV3_WRAP1_S6_CLK 74 85 #define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC 75 86 #define SE_GCC_QUPV3_WRAP1_S_AHB_CLK 76 87 88 /* SE_GCC power domains */ 89 #define SE_GCC_EMAC0_GDSC 0 90 #define SE_GCC_EMAC1_GDSC 1 91 92 /* SE_GCC resets */ 93 #define SE_GCC_EMAC0_BCR 0 94 #define SE_GCC_EMAC1_BCR 1 95 #define SE_GCC_QUPV3_WRAPPER_0_BCR 2 96 #define SE_GCC_QUPV3_WRAPPER_1_BCR 3 97 98 #endif 99