1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_MILOS_H 8 #define _DT_BINDINGS_CLK_QCOM_GCC_MILOS_H 9 10 /* GCC clocks */ 11 #define GCC_GPLL0 0 12 #define GCC_GPLL0_OUT_EVEN 1 13 #define GCC_GPLL2 2 14 #define GCC_GPLL4 3 15 #define GCC_GPLL6 4 16 #define GCC_GPLL7 5 17 #define GCC_GPLL9 6 18 #define GCC_AGGRE_NOC_PCIE_AXI_CLK 7 19 #define GCC_AGGRE_UFS_PHY_AXI_CLK 8 20 #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 9 21 #define GCC_AGGRE_USB3_PRIM_AXI_CLK 10 22 #define GCC_BOOT_ROM_AHB_CLK 11 23 #define GCC_CAMERA_AHB_CLK 12 24 #define GCC_CAMERA_HF_AXI_CLK 13 25 #define GCC_CAMERA_HF_XO_CLK 14 26 #define GCC_CAMERA_SF_AXI_CLK 15 27 #define GCC_CAMERA_SF_XO_CLK 16 28 #define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 17 29 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 18 30 #define GCC_CNOC_PCIE_SF_AXI_CLK 19 31 #define GCC_DDRSS_GPU_AXI_CLK 20 32 #define GCC_DDRSS_PCIE_SF_QTB_CLK 21 33 #define GCC_DISP_AHB_CLK 22 34 #define GCC_DISP_GPLL0_DIV_CLK_SRC 23 35 #define GCC_DISP_HF_AXI_CLK 24 36 #define GCC_DISP_XO_CLK 25 37 #define GCC_GP1_CLK 26 38 #define GCC_GP1_CLK_SRC 27 39 #define GCC_GP2_CLK 28 40 #define GCC_GP2_CLK_SRC 29 41 #define GCC_GP3_CLK 30 42 #define GCC_GP3_CLK_SRC 31 43 #define GCC_GPU_CFG_AHB_CLK 32 44 #define GCC_GPU_GPLL0_CLK_SRC 33 45 #define GCC_GPU_GPLL0_DIV_CLK_SRC 34 46 #define GCC_GPU_MEMNOC_GFX_CLK 35 47 #define GCC_GPU_SNOC_DVM_GFX_CLK 36 48 #define GCC_PCIE_0_AUX_CLK 37 49 #define GCC_PCIE_0_AUX_CLK_SRC 38 50 #define GCC_PCIE_0_CFG_AHB_CLK 39 51 #define GCC_PCIE_0_MSTR_AXI_CLK 40 52 #define GCC_PCIE_0_PHY_RCHNG_CLK 41 53 #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42 54 #define GCC_PCIE_0_PIPE_CLK 43 55 #define GCC_PCIE_0_PIPE_CLK_SRC 44 56 #define GCC_PCIE_0_PIPE_DIV2_CLK 45 57 #define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 46 58 #define GCC_PCIE_0_SLV_AXI_CLK 47 59 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 60 #define GCC_PCIE_1_AUX_CLK 49 61 #define GCC_PCIE_1_AUX_CLK_SRC 50 62 #define GCC_PCIE_1_CFG_AHB_CLK 51 63 #define GCC_PCIE_1_MSTR_AXI_CLK 52 64 #define GCC_PCIE_1_PHY_RCHNG_CLK 53 65 #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 54 66 #define GCC_PCIE_1_PIPE_CLK 55 67 #define GCC_PCIE_1_PIPE_CLK_SRC 56 68 #define GCC_PCIE_1_PIPE_DIV2_CLK 57 69 #define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 58 70 #define GCC_PCIE_1_SLV_AXI_CLK 59 71 #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 60 72 #define GCC_PCIE_RSCC_CFG_AHB_CLK 61 73 #define GCC_PCIE_RSCC_XO_CLK 62 74 #define GCC_PDM2_CLK 63 75 #define GCC_PDM2_CLK_SRC 64 76 #define GCC_PDM_AHB_CLK 65 77 #define GCC_PDM_XO4_CLK 66 78 #define GCC_QMIP_CAMERA_NRT_AHB_CLK 67 79 #define GCC_QMIP_CAMERA_RT_AHB_CLK 68 80 #define GCC_QMIP_DISP_AHB_CLK 69 81 #define GCC_QMIP_GPU_AHB_CLK 70 82 #define GCC_QMIP_PCIE_AHB_CLK 71 83 #define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 72 84 #define GCC_QMIP_VIDEO_CVP_AHB_CLK 73 85 #define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 74 86 #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 75 87 #define GCC_QUPV3_WRAP0_CORE_2X_CLK 76 88 #define GCC_QUPV3_WRAP0_CORE_CLK 77 89 #define GCC_QUPV3_WRAP0_QSPI_REF_CLK 78 90 #define GCC_QUPV3_WRAP0_QSPI_REF_CLK_SRC 79 91 #define GCC_QUPV3_WRAP0_S0_CLK 80 92 #define GCC_QUPV3_WRAP0_S0_CLK_SRC 81 93 #define GCC_QUPV3_WRAP0_S1_CLK 82 94 #define GCC_QUPV3_WRAP0_S1_CLK_SRC 83 95 #define GCC_QUPV3_WRAP0_S2_CLK 84 96 #define GCC_QUPV3_WRAP0_S2_CLK_SRC 85 97 #define GCC_QUPV3_WRAP0_S3_CLK 86 98 #define GCC_QUPV3_WRAP0_S3_CLK_SRC 87 99 #define GCC_QUPV3_WRAP0_S4_CLK 88 100 #define GCC_QUPV3_WRAP0_S4_CLK_SRC 89 101 #define GCC_QUPV3_WRAP0_S5_CLK 90 102 #define GCC_QUPV3_WRAP0_S5_CLK_SRC 91 103 #define GCC_QUPV3_WRAP0_S6_CLK 92 104 #define GCC_QUPV3_WRAP0_S6_CLK_SRC 93 105 #define GCC_QUPV3_WRAP1_CORE_2X_CLK 94 106 #define GCC_QUPV3_WRAP1_CORE_CLK 95 107 #define GCC_QUPV3_WRAP1_QSPI_REF_CLK 96 108 #define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 97 109 #define GCC_QUPV3_WRAP1_S0_CLK 98 110 #define GCC_QUPV3_WRAP1_S0_CLK_SRC 99 111 #define GCC_QUPV3_WRAP1_S1_CLK 100 112 #define GCC_QUPV3_WRAP1_S1_CLK_SRC 101 113 #define GCC_QUPV3_WRAP1_S2_CLK 102 114 #define GCC_QUPV3_WRAP1_S2_CLK_SRC 103 115 #define GCC_QUPV3_WRAP1_S3_CLK 104 116 #define GCC_QUPV3_WRAP1_S3_CLK_SRC 105 117 #define GCC_QUPV3_WRAP1_S4_CLK 106 118 #define GCC_QUPV3_WRAP1_S4_CLK_SRC 107 119 #define GCC_QUPV3_WRAP1_S5_CLK 108 120 #define GCC_QUPV3_WRAP1_S5_CLK_SRC 109 121 #define GCC_QUPV3_WRAP1_S6_CLK 110 122 #define GCC_QUPV3_WRAP1_S6_CLK_SRC 111 123 #define GCC_QUPV3_WRAP_0_M_AHB_CLK 112 124 #define GCC_QUPV3_WRAP_0_S_AHB_CLK 113 125 #define GCC_QUPV3_WRAP_1_M_AHB_CLK 114 126 #define GCC_QUPV3_WRAP_1_S_AHB_CLK 115 127 #define GCC_SDCC1_AHB_CLK 116 128 #define GCC_SDCC1_APPS_CLK 117 129 #define GCC_SDCC1_APPS_CLK_SRC 118 130 #define GCC_SDCC1_ICE_CORE_CLK 119 131 #define GCC_SDCC1_ICE_CORE_CLK_SRC 120 132 #define GCC_SDCC2_AHB_CLK 121 133 #define GCC_SDCC2_APPS_CLK 122 134 #define GCC_SDCC2_APPS_CLK_SRC 123 135 #define GCC_UFS_PHY_AHB_CLK 124 136 #define GCC_UFS_PHY_AXI_CLK 125 137 #define GCC_UFS_PHY_AXI_CLK_SRC 126 138 #define GCC_UFS_PHY_AXI_HW_CTL_CLK 127 139 #define GCC_UFS_PHY_ICE_CORE_CLK 128 140 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 129 141 #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 130 142 #define GCC_UFS_PHY_PHY_AUX_CLK 131 143 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 132 144 #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 133 145 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 134 146 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 135 147 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 136 148 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 137 149 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138 150 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 139 151 #define GCC_UFS_PHY_UNIPRO_CORE_CLK 140 152 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 141 153 #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 142 154 #define GCC_USB30_PRIM_ATB_CLK 143 155 #define GCC_USB30_PRIM_MASTER_CLK 144 156 #define GCC_USB30_PRIM_MASTER_CLK_SRC 145 157 #define GCC_USB30_PRIM_MOCK_UTMI_CLK 146 158 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 147 159 #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 148 160 #define GCC_USB30_PRIM_SLEEP_CLK 149 161 #define GCC_USB3_PRIM_PHY_AUX_CLK 150 162 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 151 163 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 152 164 #define GCC_USB3_PRIM_PHY_PIPE_CLK 153 165 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 154 166 #define GCC_VIDEO_AHB_CLK 155 167 #define GCC_VIDEO_AXI0_CLK 156 168 #define GCC_VIDEO_XO_CLK 157 169 170 /* GCC resets */ 171 #define GCC_CAMERA_BCR 0 172 #define GCC_DISPLAY_BCR 1 173 #define GCC_GPU_BCR 2 174 #define GCC_PCIE_0_BCR 3 175 #define GCC_PCIE_0_LINK_DOWN_BCR 4 176 #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 177 #define GCC_PCIE_0_PHY_BCR 6 178 #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 179 #define GCC_PCIE_1_BCR 8 180 #define GCC_PCIE_1_LINK_DOWN_BCR 9 181 #define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10 182 #define GCC_PCIE_1_PHY_BCR 11 183 #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12 184 #define GCC_PCIE_RSCC_BCR 13 185 #define GCC_PDM_BCR 14 186 #define GCC_QUPV3_WRAPPER_0_BCR 15 187 #define GCC_QUPV3_WRAPPER_1_BCR 16 188 #define GCC_QUSB2PHY_PRIM_BCR 17 189 #define GCC_QUSB2PHY_SEC_BCR 18 190 #define GCC_SDCC1_BCR 19 191 #define GCC_SDCC2_BCR 20 192 #define GCC_UFS_PHY_BCR 21 193 #define GCC_USB30_PRIM_BCR 22 194 #define GCC_USB3_DP_PHY_PRIM_BCR 23 195 #define GCC_USB3_PHY_PRIM_BCR 24 196 #define GCC_USB3PHY_PHY_PRIM_BCR 25 197 #define GCC_VIDEO_AXI0_CLK_ARES 26 198 #define GCC_VIDEO_BCR 27 199 200 /* GCC power domains */ 201 #define PCIE_0_GDSC 0 202 #define PCIE_0_PHY_GDSC 1 203 #define PCIE_1_GDSC 2 204 #define PCIE_1_PHY_GDSC 3 205 #define UFS_PHY_GDSC 4 206 #define UFS_MEM_PHY_GDSC 5 207 #define USB30_PRIM_GDSC 6 208 #define USB3_PHY_GDSC 7 209 210 #endif 211