xref: /linux/include/dt-bindings/clock/qcom,kaanapali-gpucc.h (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e)
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /*
3  * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4  */
5 
6 #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_KAANAPALI_H
7 #define _DT_BINDINGS_CLK_QCOM_GPU_CC_KAANAPALI_H
8 
9 /* GPU_CC clocks */
10 #define GPU_CC_AHB_CLK						0
11 #define GPU_CC_CB_CLK						1
12 #define GPU_CC_CX_ACCU_SHIFT_CLK				2
13 #define GPU_CC_CX_GMU_CLK					3
14 #define GPU_CC_CXO_AON_CLK					4
15 #define GPU_CC_CXO_CLK						5
16 #define GPU_CC_DEMET_CLK					6
17 #define GPU_CC_DPM_CLK						7
18 #define GPU_CC_FF_CLK_SRC					8
19 #define GPU_CC_FREQ_MEASURE_CLK					9
20 #define GPU_CC_GMU_CLK_SRC					10
21 #define GPU_CC_GPU_SMMU_VOTE_CLK				11
22 #define GPU_CC_GX_ACCU_SHIFT_CLK				12
23 #define GPU_CC_GX_GMU_CLK					13
24 #define GPU_CC_HUB_AON_CLK					14
25 #define GPU_CC_HUB_CLK_SRC					15
26 #define GPU_CC_HUB_CX_INT_CLK					16
27 #define GPU_CC_HUB_DIV_CLK_SRC					17
28 #define GPU_CC_MEMNOC_GFX_CLK					18
29 #define GPU_CC_PLL0						19
30 #define GPU_CC_PLL0_OUT_EVEN					20
31 #define GPU_CC_RSCC_HUB_AON_CLK					21
32 #define GPU_CC_RSCC_XO_AON_CLK					22
33 #define GPU_CC_SLEEP_CLK					23
34 
35 /* GPU_CC power domains */
36 #define GPU_CC_CX_GDSC						0
37 
38 /* GPU_CC resets */
39 #define GPU_CC_CB_BCR						0
40 #define GPU_CC_CX_BCR						1
41 #define GPU_CC_FAST_HUB_BCR					2
42 #define GPU_CC_FF_BCR						3
43 #define GPU_CC_GMU_BCR						4
44 #define GPU_CC_GX_BCR						5
45 #define GPU_CC_XO_BCR						6
46 
47 #endif
48