1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_IPQ5210_CMN_PLL_H 7 #define _DT_BINDINGS_CLK_QCOM_IPQ5210_CMN_PLL_H 8 9 /* Parent clock */ 10 #define IPQ5210_CMN_PLL_CLK 0 11 12 /* Fixed-rate clocks */ 13 #define IPQ5210_XO_24MHZ_CLK 1 14 #define IPQ5210_SLEEP_32KHZ_CLK 2 15 16 /* Configurable divider clocks */ 17 #define IPQ5210_NSS_CLK 3 18 #define IPQ5210_PPE_CLK 4 19 #define IPQ5210_PON_CLK 5 20 #define IPQ5210_EPHY_RAW_CLK 6 21 22 /* Gate clocks */ 23 #define IPQ5210_PCS_31P25MHZ_CLK 7 24 #define IPQ5210_ETH0_50MHZ_CLK 8 25 #define IPQ5210_ETH1_50MHZ_CLK 9 26 #define IPQ5210_ETH2_50MHZ_CLK 10 27 #define IPQ5210_EPHY_50MHZ_CLK 11 28 #define IPQ5210_ETH_25MHZ_CLK 12 29 30 #endif 31