xref: /linux/include/dt-bindings/clock/qcom,gcc-msm8952.h (revision 9c50d323ca4fe6213b827dc8b13dbb4916613319)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright 2020 Linaro Limited
4  * Copyright 2026 Muzaffer Kadir <muzafferkadir@mainlining.org>
5  */
6 
7 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8952_H
8 #define _DT_BINDINGS_CLK_MSM_GCC_8952_H
9 
10 #define GPLL0						0
11 #define GPLL0_VOTE					1
12 #define GPLL3						2
13 #define GPLL3_EARLY					3
14 #define GPLL4						4
15 #define GPLL4_VOTE					5
16 #define GPLL6						6
17 #define GPLL6_VOTE					7
18 #define CAMSS_TOP_AHB_CLK_SRC				8
19 #define APSS_AHB_CLK_SRC				9
20 #define CSI0_CLK_SRC					10
21 #define CSI1_CLK_SRC					11
22 #define GFX3D_CLK_SRC					12
23 #define VFE0_CLK_SRC					13
24 #define BLSP1_QUP1_I2C_APPS_CLK_SRC			14
25 #define BLSP1_QUP1_SPI_APPS_CLK_SRC			15
26 #define BLSP1_QUP2_I2C_APPS_CLK_SRC			16
27 #define BLSP1_QUP2_SPI_APPS_CLK_SRC			17
28 #define BLSP1_QUP3_I2C_APPS_CLK_SRC			18
29 #define BLSP1_QUP3_SPI_APPS_CLK_SRC			19
30 #define BLSP1_QUP4_I2C_APPS_CLK_SRC			20
31 #define BLSP1_QUP4_SPI_APPS_CLK_SRC			21
32 #define BLSP1_UART1_APPS_CLK_SRC			22
33 #define BLSP1_UART2_APPS_CLK_SRC			23
34 #define CCI_CLK_SRC					24
35 #define CAMSS_GP0_CLK_SRC				25
36 #define CAMSS_GP1_CLK_SRC				26
37 #define JPEG0_CLK_SRC					27
38 #define MCLK0_CLK_SRC					28
39 #define MCLK1_CLK_SRC					29
40 #define CSI0PHYTIMER_CLK_SRC				30
41 #define CSI1PHYTIMER_CLK_SRC				31
42 #define CPP_CLK_SRC					32
43 #define CRYPTO_CLK_SRC					33
44 #define GP1_CLK_SRC					34
45 #define GP2_CLK_SRC					35
46 #define GP3_CLK_SRC					36
47 #define BYTE0_CLK_SRC					37
48 #define ESC0_CLK_SRC					38
49 #define MDP_CLK_SRC					39
50 #define PCLK0_CLK_SRC					40
51 #define VSYNC_CLK_SRC					41
52 #define PDM2_CLK_SRC					42
53 #define SDCC1_APPS_CLK_SRC				43
54 #define SDCC2_APPS_CLK_SRC				44
55 #define USB_HS_SYSTEM_CLK_SRC				45
56 #define VCODEC0_CLK_SRC					46
57 #define GCC_BLSP1_AHB_CLK				47
58 #define GCC_BLSP1_QUP1_I2C_APPS_CLK			48
59 #define GCC_BLSP1_QUP1_SPI_APPS_CLK			49
60 #define GCC_BLSP1_QUP2_I2C_APPS_CLK			50
61 #define GCC_BLSP1_QUP2_SPI_APPS_CLK			51
62 #define GCC_BLSP1_QUP3_I2C_APPS_CLK			52
63 #define GCC_BLSP1_QUP3_SPI_APPS_CLK			53
64 #define GCC_BLSP1_QUP4_I2C_APPS_CLK			54
65 #define GCC_BLSP1_QUP4_SPI_APPS_CLK			55
66 #define GCC_BLSP1_UART1_APPS_CLK			56
67 #define GCC_BLSP1_UART2_APPS_CLK			57
68 #define GCC_BOOT_ROM_AHB_CLK				58
69 #define GCC_CAMSS_CCI_AHB_CLK				59
70 #define GCC_CAMSS_CCI_CLK				60
71 #define GCC_CAMSS_CSI0_AHB_CLK				61
72 #define GCC_CAMSS_CSI0_CLK				62
73 #define GCC_CAMSS_CSI0PHY_CLK				63
74 #define GCC_CAMSS_CSI0PIX_CLK				64
75 #define GCC_CAMSS_CSI0RDI_CLK				65
76 #define GCC_CAMSS_CSI1_AHB_CLK				66
77 #define GCC_CAMSS_CSI1_CLK				67
78 #define GCC_CAMSS_CSI1PHY_CLK				68
79 #define GCC_CAMSS_CSI1PIX_CLK				69
80 #define GCC_CAMSS_CSI1RDI_CLK				70
81 #define GCC_CAMSS_CSI_VFE0_CLK				71
82 #define GCC_CAMSS_GP0_CLK				72
83 #define GCC_CAMSS_GP1_CLK				73
84 #define GCC_CAMSS_ISPIF_AHB_CLK				74
85 #define GCC_CAMSS_JPEG0_CLK				75
86 #define GCC_CAMSS_JPEG_AHB_CLK				76
87 #define GCC_CAMSS_JPEG_AXI_CLK				77
88 #define GCC_CAMSS_MCLK0_CLK				78
89 #define GCC_CAMSS_MCLK1_CLK				79
90 #define GCC_CAMSS_MICRO_AHB_CLK				80
91 #define GCC_CAMSS_CSI0PHYTIMER_CLK			81
92 #define GCC_CAMSS_CSI1PHYTIMER_CLK			82
93 #define GCC_CAMSS_AHB_CLK				83
94 #define GCC_CAMSS_TOP_AHB_CLK				84
95 #define GCC_CAMSS_CPP_AHB_CLK				85
96 #define GCC_CAMSS_CPP_CLK				86
97 #define GCC_CAMSS_VFE0_CLK				87
98 #define GCC_CAMSS_VFE0_AHB_CLK				88
99 #define GCC_CAMSS_VFE0_AXI_CLK				89
100 #define GCC_CRYPTO_AHB_CLK				90
101 #define GCC_CRYPTO_AXI_CLK				91
102 #define GCC_CRYPTO_CLK					92
103 #define GCC_OXILI_GMEM_CLK				93
104 #define GCC_GP1_CLK					94
105 #define GCC_GP2_CLK					95
106 #define GCC_GP3_CLK					96
107 #define GCC_MDSS_AHB_CLK				97
108 #define GCC_MDSS_AXI_CLK				98
109 #define GCC_MDSS_BYTE0_CLK				99
110 #define GCC_MDSS_ESC0_CLK				100
111 #define GCC_MDSS_MDP_CLK				101
112 #define GCC_MDSS_PCLK0_CLK				102
113 #define GCC_MDSS_VSYNC_CLK				103
114 #define GCC_MSS_CFG_AHB_CLK				104
115 #define GCC_OXILI_AHB_CLK				105
116 #define GCC_OXILI_GFX3D_CLK				106
117 #define GCC_PDM2_CLK					107
118 #define GCC_PDM_AHB_CLK					108
119 #define GCC_PRNG_AHB_CLK				109
120 #define GCC_SDCC1_AHB_CLK				110
121 #define GCC_SDCC1_APPS_CLK				111
122 #define GCC_SDCC2_AHB_CLK				112
123 #define GCC_SDCC2_APPS_CLK				113
124 #define GCC_GTCU_AHB_CLK				114
125 #define GCC_JPEG_TBU_CLK				115
126 #define GCC_MDP_TBU_CLK					116
127 #define GCC_SMMU_CFG_CLK				117
128 #define GCC_VENUS_TBU_CLK				118
129 #define GCC_VFE_TBU_CLK					119
130 #define GCC_USB2A_PHY_SLEEP_CLK				120
131 #define GCC_USB_HS_AHB_CLK				121
132 #define GCC_USB_HS_SYSTEM_CLK				122
133 #define GCC_VENUS0_AHB_CLK				123
134 #define GCC_VENUS0_AXI_CLK				124
135 #define GCC_VENUS0_VCODEC0_CLK				125
136 #define GCC_APSS_TCU_CLK				126
137 #define GCC_GFX_TCU_CLK					127
138 #define GCC_BIMC_GFX_CLK				128
139 #define GCC_BIMC_GPU_CLK				129
140 #define GCC_MSS_Q6_BIMC_AXI_CLK				130
141 #define GCC_GFX_TBU_CLK					131
142 #define GCC_CPP_TBU_CLK					132
143 #define USB_FS_SYSTEM_CLK_SRC				133
144 #define USB_FS_IC_CLK_SRC				134
145 #define GCC_USB_FS_AHB_CLK				135
146 #define GCC_USB_FS_IC_CLK				136
147 #define GCC_USB_FS_SYSTEM_CLK				137
148 #define GCC_VENUS0_CORE0_VCODEC0_CLK			138
149 #define GCC_VENUS0_CORE1_VCODEC0_CLK			139
150 #define GCC_OXILI_TIMER_CLK				140
151 #define GCC_USB_HS_PHY_CFG_AHB_CLK			141
152 #define CSI2_CLK_SRC					142
153 #define GCC_CAMSS_CSI2_AHB_CLK				143
154 #define GCC_CAMSS_CSI2_CLK				144
155 #define GCC_CAMSS_CSI2PHY_CLK				145
156 #define GCC_CAMSS_CSI2PIX_CLK				146
157 #define GCC_CAMSS_CSI2RDI_CLK				147
158 #define SDCC1_ICE_CORE_CLK_SRC				148
159 #define GCC_SDCC1_ICE_CORE_CLK				149
160 #define BLSP2_QUP1_I2C_APPS_CLK_SRC			150
161 #define BLSP2_QUP1_SPI_APPS_CLK_SRC			151
162 #define BLSP2_QUP2_I2C_APPS_CLK_SRC			152
163 #define BLSP2_QUP2_SPI_APPS_CLK_SRC			153
164 #define BLSP2_QUP3_I2C_APPS_CLK_SRC			154
165 #define BLSP2_QUP3_SPI_APPS_CLK_SRC			155
166 #define BLSP2_QUP4_I2C_APPS_CLK_SRC			156
167 #define BLSP2_QUP4_SPI_APPS_CLK_SRC			157
168 #define BLSP2_UART1_APPS_CLK_SRC			158
169 #define BLSP2_UART2_APPS_CLK_SRC			159
170 #define GCC_BLSP2_AHB_CLK				160
171 #define GCC_BLSP2_QUP1_I2C_APPS_CLK			161
172 #define GCC_BLSP2_QUP1_SPI_APPS_CLK			162
173 #define GCC_BLSP2_QUP2_I2C_APPS_CLK			163
174 #define GCC_BLSP2_QUP2_SPI_APPS_CLK			164
175 #define GCC_BLSP2_QUP3_I2C_APPS_CLK			165
176 #define GCC_BLSP2_QUP3_SPI_APPS_CLK			166
177 #define GCC_BLSP2_QUP4_I2C_APPS_CLK			167
178 #define GCC_BLSP2_QUP4_SPI_APPS_CLK			168
179 #define GCC_BLSP2_UART1_APPS_CLK			169
180 #define GCC_BLSP2_UART2_APPS_CLK			170
181 #define VFE1_CLK_SRC					171
182 #define GCC_CAMSS_VFE1_CLK				172
183 #define GCC_CAMSS_VFE1_AHB_CLK				173
184 #define GCC_CAMSS_VFE1_AXI_CLK				174
185 #define GCC_CAMSS_CSI_VFE1_CLK				175
186 #define MCLK2_CLK_SRC					176
187 #define GCC_CAMSS_MCLK2_CLK				177
188 #define GCC_VFE1_TBU_CLK				178
189 #define GCC_IPA_TBU_CLK					179
190 #define GCC_CAMSS_CPP_AXI_CLK				180
191 
192 /* Indexes for GDSCs */
193 #define VENUS_GDSC				0
194 #define MDSS_GDSC				1
195 #define JPEG_GDSC				2
196 #define VFE0_GDSC				3
197 #define VFE1_GDSC				4
198 #define OXILI_GX_GDSC				5
199 #define VENUS_CORE0_GDSC			6
200 #define VENUS_CORE1_GDSC			7
201 #define CPP_GDSC				8
202 
203 /* Indexes for Resets */
204 #define GCC_CRYPTO_BCR				0
205 #define GCC_USB_FS_BCR				1
206 #define GCC_USB_HS_BCR				2
207 #define GCC_QUSB2_PHY_BCR			3
208 #define GCC_USB2_HS_PHY_ONLY_BCR		4
209 #define GCC_SDCC1_BCR				5
210 #define GCC_SDCC2_BCR				6
211 #define GCC_MDSS_BCR				7
212 #define GCC_CAMSS_MICRO_BCR			8
213 #define GCC_MSS_BCR				9
214 
215 #endif
216