1*fc8c21a2SXuyang Dong /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*fc8c21a2SXuyang Dong /* 3*fc8c21a2SXuyang Dong * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.. 4*fc8c21a2SXuyang Dong * All rights reserved. 5*fc8c21a2SXuyang Dong * 6*fc8c21a2SXuyang Dong * Device Tree binding constants for EIC7700 HSP clock controller. 7*fc8c21a2SXuyang Dong * 8*fc8c21a2SXuyang Dong * Authors: Xuyang Dong <dongxuyang@eswincomputing.com> 9*fc8c21a2SXuyang Dong */ 10*fc8c21a2SXuyang Dong 11*fc8c21a2SXuyang Dong #ifndef _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_ 12*fc8c21a2SXuyang Dong #define _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_ 13*fc8c21a2SXuyang Dong 14*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_FAC_CFG_DIV2 0 15*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_FAC_CFG_DIV4 1 16*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_FAC_MMC_DIV10 2 17*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_MUX_EMMC_3MUX1 3 18*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_MUX_SD0_3MUX1 4 19*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_MUX_SD1_3MUX1 5 20*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_MUX_EMMC_CQE_2MUX1 6 21*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_MUX_SD0_CQE_2MUX1 7 22*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_MUX_SD1_CQE_2MUX1 8 23*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_GATE_MSHC0_TMR 9 24*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_GATE_EMMC 10 25*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_GATE_MSHC1_TMR 11 26*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_GATE_SD0 12 27*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_GATE_MSHC2_TMR 13 28*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_GATE_SD1 14 29*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_GATE_USB0 15 30*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_GATE_USB1 16 31*fc8c21a2SXuyang Dong #define EIC7700_HSP_CLK_GATE_SATA 17 32*fc8c21a2SXuyang Dong 33*fc8c21a2SXuyang Dong #endif /* _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_ */ 34