1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.. 4 * All rights reserved. 5 * 6 * Device Tree binding constants for EIC7700 HSP clock controller. 7 * 8 * Authors: Xuyang Dong <dongxuyang@eswincomputing.com> 9 */ 10 11 #ifndef _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_ 12 #define _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_ 13 14 #define EIC7700_HSP_CLK_FAC_CFG_DIV2 0 15 #define EIC7700_HSP_CLK_FAC_CFG_DIV4 1 16 #define EIC7700_HSP_CLK_FAC_MMC_DIV10 2 17 #define EIC7700_HSP_CLK_MUX_EMMC_3MUX1 3 18 #define EIC7700_HSP_CLK_MUX_SD0_3MUX1 4 19 #define EIC7700_HSP_CLK_MUX_SD1_3MUX1 5 20 #define EIC7700_HSP_CLK_MUX_EMMC_CQE_2MUX1 6 21 #define EIC7700_HSP_CLK_MUX_SD0_CQE_2MUX1 7 22 #define EIC7700_HSP_CLK_MUX_SD1_CQE_2MUX1 8 23 #define EIC7700_HSP_CLK_GATE_MSHC0_TMR 9 24 #define EIC7700_HSP_CLK_GATE_EMMC 10 25 #define EIC7700_HSP_CLK_GATE_MSHC1_TMR 11 26 #define EIC7700_HSP_CLK_GATE_SD0 12 27 #define EIC7700_HSP_CLK_GATE_MSHC2_TMR 13 28 #define EIC7700_HSP_CLK_GATE_SD1 14 29 #define EIC7700_HSP_CLK_GATE_USB0 15 30 #define EIC7700_HSP_CLK_GATE_USB1 16 31 #define EIC7700_HSP_CLK_GATE_SATA 17 32 33 #endif /* _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_ */ 34