1*48ceae43SJoakim Zhang /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*48ceae43SJoakim Zhang /* 3*48ceae43SJoakim Zhang * Copyright 2026 Cix Technology Group Co., Ltd. 4*48ceae43SJoakim Zhang */ 5*48ceae43SJoakim Zhang 6*48ceae43SJoakim Zhang #ifndef _DT_BINDINGS_CLOCK_CIX_SKY1_AUDSS_CRU_H 7*48ceae43SJoakim Zhang #define _DT_BINDINGS_CLOCK_CIX_SKY1_AUDSS_CRU_H 8*48ceae43SJoakim Zhang 9*48ceae43SJoakim Zhang #define CLK_AUD_CLK4_DIV2 0 10*48ceae43SJoakim Zhang #define CLK_AUD_CLK4_DIV4 1 11*48ceae43SJoakim Zhang #define CLK_AUD_CLK5_DIV2 2 12*48ceae43SJoakim Zhang 13*48ceae43SJoakim Zhang #define CLK_DSP_CLK 3 14*48ceae43SJoakim Zhang #define CLK_DSP_BCLK 4 15*48ceae43SJoakim Zhang #define CLK_DSP_PBCLK 5 16*48ceae43SJoakim Zhang 17*48ceae43SJoakim Zhang #define CLK_SRAM_AXI 6 18*48ceae43SJoakim Zhang 19*48ceae43SJoakim Zhang #define CLK_HDA_SYS 7 20*48ceae43SJoakim Zhang #define CLK_HDA_HDA 8 21*48ceae43SJoakim Zhang 22*48ceae43SJoakim Zhang #define CLK_DMAC_AXI 9 23*48ceae43SJoakim Zhang 24*48ceae43SJoakim Zhang #define CLK_WDG_APB 10 25*48ceae43SJoakim Zhang #define CLK_WDG_WDG 11 26*48ceae43SJoakim Zhang 27*48ceae43SJoakim Zhang #define CLK_TIMER_APB 12 28*48ceae43SJoakim Zhang #define CLK_TIMER_TIMER 13 29*48ceae43SJoakim Zhang 30*48ceae43SJoakim Zhang #define CLK_MB_0_APB 14 /* MB0: ap->dsp */ 31*48ceae43SJoakim Zhang #define CLK_MB_1_APB 15 /* MB1: dsp->ap */ 32*48ceae43SJoakim Zhang 33*48ceae43SJoakim Zhang #define CLK_I2S0_APB 16 34*48ceae43SJoakim Zhang #define CLK_I2S1_APB 17 35*48ceae43SJoakim Zhang #define CLK_I2S2_APB 18 36*48ceae43SJoakim Zhang #define CLK_I2S3_APB 19 37*48ceae43SJoakim Zhang #define CLK_I2S4_APB 20 38*48ceae43SJoakim Zhang #define CLK_I2S5_APB 21 39*48ceae43SJoakim Zhang #define CLK_I2S6_APB 22 40*48ceae43SJoakim Zhang #define CLK_I2S7_APB 23 41*48ceae43SJoakim Zhang #define CLK_I2S8_APB 24 42*48ceae43SJoakim Zhang #define CLK_I2S9_APB 25 43*48ceae43SJoakim Zhang #define CLK_I2S0 26 44*48ceae43SJoakim Zhang #define CLK_I2S1 27 45*48ceae43SJoakim Zhang #define CLK_I2S2 28 46*48ceae43SJoakim Zhang #define CLK_I2S3 29 47*48ceae43SJoakim Zhang #define CLK_I2S4 30 48*48ceae43SJoakim Zhang #define CLK_I2S5 31 49*48ceae43SJoakim Zhang #define CLK_I2S6 32 50*48ceae43SJoakim Zhang #define CLK_I2S7 33 51*48ceae43SJoakim Zhang #define CLK_I2S8 34 52*48ceae43SJoakim Zhang #define CLK_I2S9 35 53*48ceae43SJoakim Zhang 54*48ceae43SJoakim Zhang #define CLK_MCLK0 36 55*48ceae43SJoakim Zhang #define CLK_MCLK1 37 56*48ceae43SJoakim Zhang #define CLK_MCLK2 38 57*48ceae43SJoakim Zhang #define CLK_MCLK3 39 58*48ceae43SJoakim Zhang #define CLK_MCLK4 40 59*48ceae43SJoakim Zhang 60*48ceae43SJoakim Zhang #endif 61