1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright 2026 Cix Technology Group Co., Ltd. 4 */ 5 6 #ifndef _DT_BINDINGS_CLOCK_CIX_SKY1_AUDSS_CRU_H 7 #define _DT_BINDINGS_CLOCK_CIX_SKY1_AUDSS_CRU_H 8 9 #define CLK_AUD_CLK4_DIV2 0 10 #define CLK_AUD_CLK4_DIV4 1 11 #define CLK_AUD_CLK5_DIV2 2 12 13 #define CLK_DSP_CLK 3 14 #define CLK_DSP_BCLK 4 15 #define CLK_DSP_PBCLK 5 16 17 #define CLK_SRAM_AXI 6 18 19 #define CLK_HDA_SYS 7 20 #define CLK_HDA_HDA 8 21 22 #define CLK_DMAC_AXI 9 23 24 #define CLK_WDG_APB 10 25 #define CLK_WDG_WDG 11 26 27 #define CLK_TIMER_APB 12 28 #define CLK_TIMER_TIMER 13 29 30 #define CLK_MB_0_APB 14 /* MB0: ap->dsp */ 31 #define CLK_MB_1_APB 15 /* MB1: dsp->ap */ 32 33 #define CLK_I2S0_APB 16 34 #define CLK_I2S1_APB 17 35 #define CLK_I2S2_APB 18 36 #define CLK_I2S3_APB 19 37 #define CLK_I2S4_APB 20 38 #define CLK_I2S5_APB 21 39 #define CLK_I2S6_APB 22 40 #define CLK_I2S7_APB 23 41 #define CLK_I2S8_APB 24 42 #define CLK_I2S9_APB 25 43 #define CLK_I2S0 26 44 #define CLK_I2S1 27 45 #define CLK_I2S2 28 46 #define CLK_I2S3 29 47 #define CLK_I2S4 30 48 #define CLK_I2S5 31 49 #define CLK_I2S6 32 50 #define CLK_I2S7 33 51 #define CLK_I2S8 34 52 #define CLK_I2S9 35 53 54 #define CLK_MCLK0 36 55 #define CLK_MCLK1 37 56 #define CLK_MCLK2 38 57 #define CLK_MCLK3 39 58 #define CLK_MCLK4 40 59 60 #endif 61