1 /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 /* 3 * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved 4 */ 5 6 #ifndef __T7_SCMI_CLKC_H 7 #define __T7_SCMI_CLKC_H 8 9 #define CLKID_DDR_PLL_OSC 0 10 #define CLKID_AUD_PLL_OSC 1 11 #define CLKID_TOP_PLL_OSC 2 12 #define CLKID_TCON_PLL_OSC 3 13 #define CLKID_USB_PLL0_OSC 4 14 #define CLKID_USB_PLL1_OSC 5 15 #define CLKID_MCLK_PLL_OSC 6 16 #define CLKID_PCIE_OSC 7 17 #define CLKID_ETH_PLL_OSC 8 18 #define CLKID_PCIE_REFCLK_PLL_OSC 9 19 #define CLKID_EARC_OSC 10 20 #define CLKID_SYS1_PLL_OSC 11 21 #define CLKID_HDMI_PLL_OSC 12 22 #define CLKID_SYS_CLK 13 23 #define CLKID_AXI_CLK 14 24 #define CLKID_FIXED_PLL_DCO 15 25 #define CLKID_FIXED_PLL 16 26 #define CLKID_FCLK_DIV2_DIV 17 27 #define CLKID_FCLK_DIV2 18 28 #define CLKID_FCLK_DIV2P5_DIV 19 29 #define CLKID_FCLK_DIV2P5 20 30 #define CLKID_FCLK_DIV3_DIV 21 31 #define CLKID_FCLK_DIV3 22 32 #define CLKID_FCLK_DIV4_DIV 23 33 #define CLKID_FCLK_DIV4 24 34 #define CLKID_FCLK_DIV5_DIV 25 35 #define CLKID_FCLK_DIV5 26 36 #define CLKID_FCLK_DIV7_DIV 27 37 #define CLKID_FCLK_DIV7 28 38 #define CLKID_FCLK_50M_DIV 29 39 #define CLKID_FCLK_50M 30 40 #define CLKID_CPU_CLK 31 41 #define CLKID_A73_CLK 32 42 #define CLKID_CPU_CLK_DIV16_DIV 33 43 #define CLKID_CPU_CLK_DIV16 34 44 #define CLKID_A73_CLK_DIV16_DIV 35 45 #define CLKID_A73_CLK_DIV16 36 46 47 #endif /* __T7_SCMI_CLKC_H */ 48