1*2c0c1e9aSJani Nikula /* SPDX-License-Identifier: MIT */ 2*2c0c1e9aSJani Nikula /* 3*2c0c1e9aSJani Nikula * Copyright © 2022 Intel Corporation 4*2c0c1e9aSJani Nikula */ 5*2c0c1e9aSJani Nikula 6*2c0c1e9aSJani Nikula #ifndef _VLV_IOSF_SB_REGS_H_ 7*2c0c1e9aSJani Nikula #define _VLV_IOSF_SB_REGS_H_ 8*2c0c1e9aSJani Nikula 9*2c0c1e9aSJani Nikula enum vlv_iosf_sb_unit { 10*2c0c1e9aSJani Nikula VLV_IOSF_SB_BUNIT, 11*2c0c1e9aSJani Nikula VLV_IOSF_SB_CCK, 12*2c0c1e9aSJani Nikula VLV_IOSF_SB_CCU, 13*2c0c1e9aSJani Nikula VLV_IOSF_SB_DPIO, 14*2c0c1e9aSJani Nikula VLV_IOSF_SB_DPIO_2, 15*2c0c1e9aSJani Nikula VLV_IOSF_SB_FLISDSI, 16*2c0c1e9aSJani Nikula VLV_IOSF_SB_GPIO, 17*2c0c1e9aSJani Nikula VLV_IOSF_SB_NC, 18*2c0c1e9aSJani Nikula VLV_IOSF_SB_PUNIT, 19*2c0c1e9aSJani Nikula }; 20*2c0c1e9aSJani Nikula 21*2c0c1e9aSJani Nikula /* See configdb bunit SB addr map */ 22*2c0c1e9aSJani Nikula #define BUNIT_REG_BISOC 0x11 23*2c0c1e9aSJani Nikula 24*2c0c1e9aSJani Nikula /* PUNIT_REG_*SSPM0 */ 25*2c0c1e9aSJani Nikula #define _SSPM0_SSC(val) ((val) << 0) 26*2c0c1e9aSJani Nikula #define SSPM0_SSC_MASK _SSPM0_SSC(0x3) 27*2c0c1e9aSJani Nikula #define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0) 28*2c0c1e9aSJani Nikula #define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1) 29*2c0c1e9aSJani Nikula #define SSPM0_SSC_RESET _SSPM0_SSC(0x2) 30*2c0c1e9aSJani Nikula #define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3) 31*2c0c1e9aSJani Nikula #define _SSPM0_SSS(val) ((val) << 24) 32*2c0c1e9aSJani Nikula #define SSPM0_SSS_MASK _SSPM0_SSS(0x3) 33*2c0c1e9aSJani Nikula #define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0) 34*2c0c1e9aSJani Nikula #define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1) 35*2c0c1e9aSJani Nikula #define SSPM0_SSS_RESET _SSPM0_SSS(0x2) 36*2c0c1e9aSJani Nikula #define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3) 37*2c0c1e9aSJani Nikula 38*2c0c1e9aSJani Nikula /* PUNIT_REG_*SSPM1 */ 39*2c0c1e9aSJani Nikula #define SSPM1_FREQSTAT_SHIFT 24 40*2c0c1e9aSJani Nikula #define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT) 41*2c0c1e9aSJani Nikula #define SSPM1_FREQGUAR_SHIFT 8 42*2c0c1e9aSJani Nikula #define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT) 43*2c0c1e9aSJani Nikula #define SSPM1_FREQ_SHIFT 0 44*2c0c1e9aSJani Nikula #define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT) 45*2c0c1e9aSJani Nikula 46*2c0c1e9aSJani Nikula #define PUNIT_REG_VEDSSPM0 0x32 47*2c0c1e9aSJani Nikula #define PUNIT_REG_VEDSSPM1 0x33 48*2c0c1e9aSJani Nikula 49*2c0c1e9aSJani Nikula #define PUNIT_REG_DSPSSPM 0x36 50*2c0c1e9aSJani Nikula #define DSPFREQSTAT_SHIFT_CHV 24 51*2c0c1e9aSJani Nikula #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 52*2c0c1e9aSJani Nikula #define DSPFREQGUAR_SHIFT_CHV 8 53*2c0c1e9aSJani Nikula #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 54*2c0c1e9aSJani Nikula #define DSPFREQSTAT_SHIFT 30 55*2c0c1e9aSJani Nikula #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 56*2c0c1e9aSJani Nikula #define DSPFREQGUAR_SHIFT 14 57*2c0c1e9aSJani Nikula #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 58*2c0c1e9aSJani Nikula #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ 59*2c0c1e9aSJani Nikula #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ 60*2c0c1e9aSJani Nikula #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ 61*2c0c1e9aSJani Nikula #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 62*2c0c1e9aSJani Nikula #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 63*2c0c1e9aSJani Nikula #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 64*2c0c1e9aSJani Nikula #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 65*2c0c1e9aSJani Nikula #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 66*2c0c1e9aSJani Nikula #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 67*2c0c1e9aSJani Nikula #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 68*2c0c1e9aSJani Nikula #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 69*2c0c1e9aSJani Nikula #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 70*2c0c1e9aSJani Nikula #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 71*2c0c1e9aSJani Nikula #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 72*2c0c1e9aSJani Nikula #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 73*2c0c1e9aSJani Nikula 74*2c0c1e9aSJani Nikula #define PUNIT_REG_ISPSSPM0 0x39 75*2c0c1e9aSJani Nikula #define PUNIT_REG_ISPSSPM1 0x3a 76*2c0c1e9aSJani Nikula 77*2c0c1e9aSJani Nikula #define PUNIT_REG_PWRGT_CTRL 0x60 78*2c0c1e9aSJani Nikula #define PUNIT_REG_PWRGT_STATUS 0x61 79*2c0c1e9aSJani Nikula #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2)) 80*2c0c1e9aSJani Nikula #define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2)) 81*2c0c1e9aSJani Nikula #define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2)) 82*2c0c1e9aSJani Nikula #define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2)) 83*2c0c1e9aSJani Nikula #define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2)) 84*2c0c1e9aSJani Nikula 85*2c0c1e9aSJani Nikula #define PUNIT_PWGT_IDX_RENDER 0 86*2c0c1e9aSJani Nikula #define PUNIT_PWGT_IDX_MEDIA 1 87*2c0c1e9aSJani Nikula #define PUNIT_PWGT_IDX_DISP2D 3 88*2c0c1e9aSJani Nikula #define PUNIT_PWGT_IDX_DPIO_CMN_BC 5 89*2c0c1e9aSJani Nikula #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6 90*2c0c1e9aSJani Nikula #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7 91*2c0c1e9aSJani Nikula #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8 92*2c0c1e9aSJani Nikula #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9 93*2c0c1e9aSJani Nikula #define PUNIT_PWGT_IDX_DPIO_RX0 10 94*2c0c1e9aSJani Nikula #define PUNIT_PWGT_IDX_DPIO_RX1 11 95*2c0c1e9aSJani Nikula #define PUNIT_PWGT_IDX_DPIO_CMN_D 12 96*2c0c1e9aSJani Nikula 97*2c0c1e9aSJani Nikula #define PUNIT_REG_GPU_LFM 0xd3 98*2c0c1e9aSJani Nikula #define PUNIT_REG_GPU_FREQ_REQ 0xd4 99*2c0c1e9aSJani Nikula #define PUNIT_REG_GPU_FREQ_STS 0xd8 100*2c0c1e9aSJani Nikula #define GPLLENABLE (1 << 4) 101*2c0c1e9aSJani Nikula #define GENFREQSTATUS (1 << 0) 102*2c0c1e9aSJani Nikula #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 103*2c0c1e9aSJani Nikula #define PUNIT_REG_CZ_TIMESTAMP 0xce 104*2c0c1e9aSJani Nikula 105*2c0c1e9aSJani Nikula #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 106*2c0c1e9aSJani Nikula #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 107*2c0c1e9aSJani Nikula 108*2c0c1e9aSJani Nikula #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 109*2c0c1e9aSJani Nikula #define FB_GFX_FREQ_FUSE_MASK 0xff 110*2c0c1e9aSJani Nikula #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 111*2c0c1e9aSJani Nikula #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 112*2c0c1e9aSJani Nikula #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 113*2c0c1e9aSJani Nikula 114*2c0c1e9aSJani Nikula #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 115*2c0c1e9aSJani Nikula #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 116*2c0c1e9aSJani Nikula 117*2c0c1e9aSJani Nikula #define PUNIT_REG_DDR_SETUP2 0x139 118*2c0c1e9aSJani Nikula #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) 119*2c0c1e9aSJani Nikula #define FORCE_DDR_LOW_FREQ (1 << 1) 120*2c0c1e9aSJani Nikula #define FORCE_DDR_HIGH_FREQ (1 << 0) 121*2c0c1e9aSJani Nikula 122*2c0c1e9aSJani Nikula #define PUNIT_GPU_STATUS_REG 0xdb 123*2c0c1e9aSJani Nikula #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 124*2c0c1e9aSJani Nikula #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 125*2c0c1e9aSJani Nikula #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 126*2c0c1e9aSJani Nikula #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 127*2c0c1e9aSJani Nikula 128*2c0c1e9aSJani Nikula #define PUNIT_GPU_DUTYCYCLE_REG 0xdf 129*2c0c1e9aSJani Nikula #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 130*2c0c1e9aSJani Nikula #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 131*2c0c1e9aSJani Nikula 132*2c0c1e9aSJani Nikula #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 133*2c0c1e9aSJani Nikula #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 134*2c0c1e9aSJani Nikula #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 135*2c0c1e9aSJani Nikula #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 136*2c0c1e9aSJani Nikula #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 137*2c0c1e9aSJani Nikula #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 138*2c0c1e9aSJani Nikula #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 139*2c0c1e9aSJani Nikula #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 140*2c0c1e9aSJani Nikula #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 141*2c0c1e9aSJani Nikula #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 142*2c0c1e9aSJani Nikula 143*2c0c1e9aSJani Nikula #define VLV_TURBO_SOC_OVERRIDE 0x04 144*2c0c1e9aSJani Nikula #define VLV_OVERRIDE_EN 1 145*2c0c1e9aSJani Nikula #define VLV_SOC_TDP_EN (1 << 1) 146*2c0c1e9aSJani Nikula #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) 147*2c0c1e9aSJani Nikula #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) 148*2c0c1e9aSJani Nikula 149*2c0c1e9aSJani Nikula /* vlv2 north clock has */ 150*2c0c1e9aSJani Nikula #define CCK_FUSE_REG 0x8 151*2c0c1e9aSJani Nikula #define CCK_FUSE_HPLL_FREQ_MASK 0x3 152*2c0c1e9aSJani Nikula #define CCK_REG_DSI_PLL_FUSE 0x44 153*2c0c1e9aSJani Nikula #define CCK_REG_DSI_PLL_CONTROL 0x48 154*2c0c1e9aSJani Nikula #define DSI_PLL_VCO_EN (1 << 31) 155*2c0c1e9aSJani Nikula #define DSI_PLL_LDO_GATE (1 << 30) 156*2c0c1e9aSJani Nikula #define DSI_PLL_P1_POST_DIV_SHIFT 17 157*2c0c1e9aSJani Nikula #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 158*2c0c1e9aSJani Nikula #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 159*2c0c1e9aSJani Nikula #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 160*2c0c1e9aSJani Nikula #define DSI_PLL_MUX_MASK (3 << 9) 161*2c0c1e9aSJani Nikula #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 162*2c0c1e9aSJani Nikula #define DSI_PLL_MUX_DSI0_CCK (1 << 10) 163*2c0c1e9aSJani Nikula #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 164*2c0c1e9aSJani Nikula #define DSI_PLL_MUX_DSI1_CCK (1 << 9) 165*2c0c1e9aSJani Nikula #define DSI_PLL_CLK_GATE_MASK (0xf << 5) 166*2c0c1e9aSJani Nikula #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 167*2c0c1e9aSJani Nikula #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 168*2c0c1e9aSJani Nikula #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 169*2c0c1e9aSJani Nikula #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 170*2c0c1e9aSJani Nikula #define DSI_PLL_LOCK (1 << 0) 171*2c0c1e9aSJani Nikula #define CCK_REG_DSI_PLL_DIVIDER 0x4c 172*2c0c1e9aSJani Nikula #define DSI_PLL_LFSR (1 << 31) 173*2c0c1e9aSJani Nikula #define DSI_PLL_FRACTION_EN (1 << 30) 174*2c0c1e9aSJani Nikula #define DSI_PLL_FRAC_COUNTER_SHIFT 27 175*2c0c1e9aSJani Nikula #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 176*2c0c1e9aSJani Nikula #define DSI_PLL_USYNC_CNT_SHIFT 18 177*2c0c1e9aSJani Nikula #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 178*2c0c1e9aSJani Nikula #define DSI_PLL_N1_DIV_SHIFT 16 179*2c0c1e9aSJani Nikula #define DSI_PLL_N1_DIV_MASK (3 << 16) 180*2c0c1e9aSJani Nikula #define DSI_PLL_M1_DIV_SHIFT 0 181*2c0c1e9aSJani Nikula #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 182*2c0c1e9aSJani Nikula #define CCK_CZ_CLOCK_CONTROL 0x62 183*2c0c1e9aSJani Nikula #define CCK_GPLL_CLOCK_CONTROL 0x67 184*2c0c1e9aSJani Nikula #define CCK_DISPLAY_CLOCK_CONTROL 0x6b 185*2c0c1e9aSJani Nikula #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c 186*2c0c1e9aSJani Nikula #define CCK_TRUNK_FORCE_ON (1 << 17) 187*2c0c1e9aSJani Nikula #define CCK_TRUNK_FORCE_OFF (1 << 16) 188*2c0c1e9aSJani Nikula #define CCK_FREQUENCY_STATUS (0x1f << 8) 189*2c0c1e9aSJani Nikula #define CCK_FREQUENCY_STATUS_SHIFT 8 190*2c0c1e9aSJani Nikula #define CCK_FREQUENCY_VALUES (0x1f << 0) 191*2c0c1e9aSJani Nikula 192*2c0c1e9aSJani Nikula #endif /* _VLV_IOSF_SB_REGS_H_ */ 193