1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef _VLV_IOSF_SB_REGS_H_ 7 #define _VLV_IOSF_SB_REGS_H_ 8 9 enum vlv_iosf_sb_unit { 10 VLV_IOSF_SB_BUNIT, 11 VLV_IOSF_SB_CCK, 12 VLV_IOSF_SB_CCU, 13 VLV_IOSF_SB_DPIO, 14 VLV_IOSF_SB_DPIO_2, 15 VLV_IOSF_SB_FLISDSI, 16 VLV_IOSF_SB_GPIO, 17 VLV_IOSF_SB_NC, 18 VLV_IOSF_SB_PUNIT, 19 }; 20 21 /* See configdb bunit SB addr map */ 22 #define BUNIT_REG_BISOC 0x11 23 24 /* PUNIT_REG_*SSPM0 */ 25 #define _SSPM0_SSC(val) ((val) << 0) 26 #define SSPM0_SSC_MASK _SSPM0_SSC(0x3) 27 #define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0) 28 #define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1) 29 #define SSPM0_SSC_RESET _SSPM0_SSC(0x2) 30 #define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3) 31 #define _SSPM0_SSS(val) ((val) << 24) 32 #define SSPM0_SSS_MASK _SSPM0_SSS(0x3) 33 #define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0) 34 #define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1) 35 #define SSPM0_SSS_RESET _SSPM0_SSS(0x2) 36 #define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3) 37 38 /* PUNIT_REG_*SSPM1 */ 39 #define SSPM1_FREQSTAT_SHIFT 24 40 #define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT) 41 #define SSPM1_FREQGUAR_SHIFT 8 42 #define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT) 43 #define SSPM1_FREQ_SHIFT 0 44 #define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT) 45 46 #define PUNIT_REG_VEDSSPM0 0x32 47 #define PUNIT_REG_VEDSSPM1 0x33 48 49 #define PUNIT_REG_DSPSSPM 0x36 50 #define DSPFREQSTAT_SHIFT_CHV 24 51 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 52 #define DSPFREQGUAR_SHIFT_CHV 8 53 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 54 #define DSPFREQSTAT_SHIFT 30 55 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 56 #define DSPFREQGUAR_SHIFT 14 57 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 58 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ 59 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ 60 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ 61 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 62 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 63 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 64 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 65 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 66 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 67 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 68 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 69 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 70 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 71 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 72 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 73 74 #define PUNIT_REG_ISPSSPM0 0x39 75 #define PUNIT_REG_ISPSSPM1 0x3a 76 77 #define PUNIT_REG_PWRGT_CTRL 0x60 78 #define PUNIT_REG_PWRGT_STATUS 0x61 79 #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2)) 80 #define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2)) 81 #define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2)) 82 #define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2)) 83 #define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2)) 84 85 #define PUNIT_PWGT_IDX_RENDER 0 86 #define PUNIT_PWGT_IDX_MEDIA 1 87 #define PUNIT_PWGT_IDX_DISP2D 3 88 #define PUNIT_PWGT_IDX_DPIO_CMN_BC 5 89 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6 90 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7 91 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8 92 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9 93 #define PUNIT_PWGT_IDX_DPIO_RX0 10 94 #define PUNIT_PWGT_IDX_DPIO_RX1 11 95 #define PUNIT_PWGT_IDX_DPIO_CMN_D 12 96 97 #define PUNIT_REG_GPU_LFM 0xd3 98 #define PUNIT_REG_GPU_FREQ_REQ 0xd4 99 #define PUNIT_REG_GPU_FREQ_STS 0xd8 100 #define GPLLENABLE (1 << 4) 101 #define GENFREQSTATUS (1 << 0) 102 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 103 #define PUNIT_REG_CZ_TIMESTAMP 0xce 104 105 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 106 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 107 108 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 109 #define FB_GFX_FREQ_FUSE_MASK 0xff 110 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 111 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 112 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 113 114 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 115 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 116 117 #define PUNIT_REG_DDR_SETUP2 0x139 118 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) 119 #define FORCE_DDR_LOW_FREQ (1 << 1) 120 #define FORCE_DDR_HIGH_FREQ (1 << 0) 121 122 #define PUNIT_GPU_STATUS_REG 0xdb 123 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 124 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 125 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 126 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 127 128 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf 129 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 130 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 131 132 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 133 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 134 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 135 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 136 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 137 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 138 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 139 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 140 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 141 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 142 143 #define VLV_TURBO_SOC_OVERRIDE 0x04 144 #define VLV_OVERRIDE_EN 1 145 #define VLV_SOC_TDP_EN (1 << 1) 146 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) 147 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) 148 149 /* vlv2 north clock has */ 150 #define CCK_FUSE_REG 0x8 151 #define CCK_FUSE_HPLL_FREQ_MASK 0x3 152 #define CCK_REG_DSI_PLL_FUSE 0x44 153 #define CCK_REG_DSI_PLL_CONTROL 0x48 154 #define DSI_PLL_VCO_EN (1 << 31) 155 #define DSI_PLL_LDO_GATE (1 << 30) 156 #define DSI_PLL_P1_POST_DIV_SHIFT 17 157 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 158 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 159 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 160 #define DSI_PLL_MUX_MASK (3 << 9) 161 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 162 #define DSI_PLL_MUX_DSI0_CCK (1 << 10) 163 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 164 #define DSI_PLL_MUX_DSI1_CCK (1 << 9) 165 #define DSI_PLL_CLK_GATE_MASK (0xf << 5) 166 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 167 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 168 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 169 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 170 #define DSI_PLL_LOCK (1 << 0) 171 #define CCK_REG_DSI_PLL_DIVIDER 0x4c 172 #define DSI_PLL_LFSR (1 << 31) 173 #define DSI_PLL_FRACTION_EN (1 << 30) 174 #define DSI_PLL_FRAC_COUNTER_SHIFT 27 175 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 176 #define DSI_PLL_USYNC_CNT_SHIFT 18 177 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 178 #define DSI_PLL_N1_DIV_SHIFT 16 179 #define DSI_PLL_N1_DIV_MASK (3 << 16) 180 #define DSI_PLL_M1_DIV_SHIFT 0 181 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 182 #define CCK_CZ_CLOCK_CONTROL 0x62 183 #define CCK_GPLL_CLOCK_CONTROL 0x67 184 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b 185 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c 186 #define CCK_TRUNK_FORCE_ON (1 << 17) 187 #define CCK_TRUNK_FORCE_OFF (1 << 16) 188 #define CCK_FREQUENCY_STATUS (0x1f << 8) 189 #define CCK_FREQUENCY_STATUS_SHIFT 8 190 #define CCK_FREQUENCY_VALUES (0x1f << 0) 191 192 #endif /* _VLV_IOSF_SB_REGS_H_ */ 193