1*a8454813SUma Shankar /* SPDX-License-Identifier: MIT */ 2*a8454813SUma Shankar /* Copyright © 2026 Intel Corporation */ 3*a8454813SUma Shankar 4*a8454813SUma Shankar #ifndef _INTEL_GMD_MISC_REGS_H_ 5*a8454813SUma Shankar #define _INTEL_GMD_MISC_REGS_H_ 6*a8454813SUma Shankar 7*a8454813SUma Shankar #define DISP_ARB_CTL _MMIO(0x45000) 8*a8454813SUma Shankar #define DISP_FBC_MEMORY_WAKE REG_BIT(31) 9*a8454813SUma Shankar #define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13) 10*a8454813SUma Shankar #define DISP_FBC_WM_DIS REG_BIT(15) 11*a8454813SUma Shankar 12*a8454813SUma Shankar #define INSTPM _MMIO(0x20c0) 13*a8454813SUma Shankar #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 14*a8454813SUma Shankar #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 15*a8454813SUma Shankar will not assert AGPBUSY# and will only 16*a8454813SUma Shankar be delivered when out of C3. */ 17*a8454813SUma Shankar #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 18*a8454813SUma Shankar #define INSTPM_TLB_INVALIDATE (1 << 9) 19*a8454813SUma Shankar #define INSTPM_SYNC_FLUSH (1 << 5) 20*a8454813SUma Shankar 21*a8454813SUma Shankar #endif 22